子分类：
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | MODEM AND RF CHIPS, APPLICATION PROCESSOR INCLUDING THE SAME AND OPERATING METHOD THEREOF | US16037024 | 2018-07-17 | US20180323820A1 | 2018-11-08 | JUN-HO HUH; HO-RANG JANG; SEOK-CHAN KIM; IN-TAE KANG; SANG-HEON LEE; KWAN-YEOB CHAE; JUNE-HEE LEE; SANG-HUNE PARK; JAE-CHOL LEE; HYUNG-KWEON LEE |
| A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal. | ||||||
| 42 | Comparator, AD converter, semiconductor integrated circuit, and rotation detector | US15651075 | 2017-07-17 | US10110215B2 | 2018-10-23 | Hideki Shimauchi; Kanji Kitamura; Mutsuo Daito; Akio Kamimurai; Masatoshi Uchino; Yoshinori Tatenuma; Akira Koshimizu |
| Provided is a comparator configured to compare input voltages, which are input to a first dynamic comparator and a second dynamic comparator, with a reference voltage, select either an output signal of the first dynamic comparator or an output signal of the second dynamic comparator based on the comparison result, output the selected output signal, and control clock signals, which are input to the first dynamic comparator and the second dynamic comparator respectively, based on the comparison result, so as to stop the operation of the dynamic comparator of which output signal is not selected. | ||||||
| 43 | METHOD AND APPARATUS FOR REDUCING IMPACT OF TRANSISTOR RANDOM MISMATCH IN CIRCUITS | US15482020 | 2017-04-07 | US20180294806A1 | 2018-10-11 | Dong Pan; John D. Porter |
| An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase. | ||||||
| 44 | Method and apparatus for reducing impact of transistor random mismatch in circuits | US15482020 | 2017-04-07 | US10097169B1 | 2018-10-09 | Dong Pan; John D. Porter |
| An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase. | ||||||
| 45 | Fast settling capacitive gain amplifier circuit | US15600484 | 2017-05-19 | US10044327B2 | 2018-08-07 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 46 | FAST SETTLING CAPACITIVE GAIN AMPLIFIER CIRCUIT | US15600484 | 2017-05-19 | US20180076779A1 | 2018-03-15 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 47 | Medical device identifier | US13942465 | 2013-07-15 | US09649165B2 | 2017-05-16 | Rodney P. Horton; John Anthony Pearce; Jonathan Walker Valvano |
| A medical device identifier can identify an implanted medical device. In one example arrangement, the medical device identifier sends electromagnetic signals to the implanted device according to one or more stored digitized waveforms. The device then senses any returned electromagnetic signals, and identifies the implanted device based on the returned electromagnetic signals. The medical device identifier may generate the electromagnetic signals from the stored digitized waveforms using an analog-to-digital converter, and may compare the returned electromagnetic signals with one or more stored digital templates corresponding to different device manufacturers. The comparison may be performed using cross correlation. In another aspect, a portal device includes an identification subsystem for identifying the provider of a medical device, and a communication subsystem for establishing two-way communication a call center servicing medical devices from an identified provider. The portal device may relay information between the medical device and the identified provider. | ||||||
| 48 | Power router apparatus for generating code-modulated powers | US15270919 | 2016-09-20 | US09641188B1 | 2017-05-02 | Atsushi Yamamoto; Shoichi Hara; Taiki Nishimoto; Kohei Masuda |
| A power router apparatus includes: a power divider that divides predetermined power into a plurality of divided powers including first divided power and second divided power; a first code modulator that code-modulates the first divided power with a first modulation code to generate first code-modulated power, which is alternating-current power; and a second code modulator that code-modulates the second divided power with a second modulation code to generate second code-modulated power, which is alternating-current power. | ||||||
| 49 | Dynamic offset cancellation in sigma-delta converter | US14811311 | 2015-07-28 | US09385746B1 | 2016-07-05 | Gek Yong Ng; Qian Tao |
| A sigma-delta converter, analog-to-digital conversion system, and an Integrated Circuit (IC) chip are disclosed that include a main sigma-delta modulator and an auxiliary sigma-delta modulator. The auxiliary sigma-delta modulator is electrically matched with the main sigma-delta modulator and is configured to generate an output that is incorporated into a feedback loop of the main sigma-delta modulator to enable the main sigma-delta modulator to adjust an offset signal applied at a main analog channel. | ||||||
| 50 | Noise shaping for digital pulse-width modulators | US14691084 | 2015-04-20 | US09287892B2 | 2016-03-15 | Eric Soenen; Alan Roth; Martin Kinyua; Justin Shi; Justin Gaither |
| A circuit includes an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a digital filter configured to filter the digital output and a noise shaper. The noise shaper is configured to truncate the filtered digital output and generate a noise shaper output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC) configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output. | ||||||
| 51 | ASYNCHRONOUS PULSE MODULATION FOR THRESHOLD-BASED SIGNAL CODING | US14513997 | 2014-10-14 | US20150372805A1 | 2015-12-24 | Young Cheul YOON |
| A method of signal processing includes comparing an input signal with one or more positive threshold values and one or more negative threshold values. The method also includes generating an output signal based on the comparison of the input signal with the positive threshold(s) and negative threshold(s). The method further includes feeding the output signal back into a decaying reconstruction filter to create a reconstructed signal and combining the reconstructed signal with the input signal. | ||||||
| 52 | SYSTEMS AND METHODS FOR COMPRESSING A DIGITAL SIGNAL IN A DIGITAL MICROPHONE SYSTEM | US14247771 | 2014-04-08 | US20140301572A1 | 2014-10-09 | John L. Melanson; John C. Tucker |
| In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a first digital signal having a plurality (e.g., more than 3) of quantization levels, and in the digital domain, process the first digital signal to compress the first digital signal into a second digital signal having fewer quantization levels (e.g., +1, 0, −1) than that of the first digital signal. | ||||||
| 53 | Phase-based analog-to-digital conversion | US13922927 | 2013-06-20 | US08797194B2 | 2014-08-05 | Yiqiao Lin; Mohammed Ismail El-nagger |
| One embodiment includes a phase-based analog-to-digital converter (ADC) system. The system includes a voltage-to-phase converter configured to convert an input voltage to a phase difference corresponding to a phase-delay with respect to an input clock signal that is based on a magnitude of the input voltage. The system also includes a phase-to-digital converter configured to convert the phase difference into a digital output signal having a digital value corresponding to a magnitude of the phase difference. | ||||||
| 54 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS | US13619034 | 2012-09-14 | US20130009795A1 | 2013-01-10 | Eric SOENEN; Alan ROTH; Martin KINYUA; Justin SHI; Justin GAITHER |
| A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output. | ||||||
| 55 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS | US12959869 | 2010-12-03 | US20110187566A1 | 2011-08-04 | Eric SOENEN; Alan ROTH; Martin KINYUA; Justin SHI; Justin GAITHER |
| A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected. | ||||||
| 56 | A/D or D/A conversion using distribution of differential waveforms to interleaved converters | US196071 | 1994-06-07 | US5537113A | 1996-07-16 | Masayuki Kawabata |
| To implement a high-speed, high-resolution A/D (or D/A) converter, a differential waveform of an analog (or digital) waveform signal is generated by a differential waveform generating part 10, the differential waveform is distributed to N integrators 14.sub.1 through 14.sub.N in a repeating cyclic order at the timing of a clock CK.sub.0, N being an integer equal to or greater than 2, and the integrator outputs are converted by converting parts 15.sub.1 through 15.sub.N to digital (or analog) signals. These converted outputs are added together by an adder 16, whose output is provided as a digital (or analog) waveform signal. | ||||||
| 57 | System for processing slope and duration information contained in complex waveforms | US3749834D | 1971-05-11 | US3749834A | 1973-07-31 | BRIAN A; ELLIS E |
| A transmission system for transmitting information contained in a complex waveform includes a transmitter in which the individual slopes forming the complex wave and the duration of these slopes are determined and converted into coded signals. These signals are transmitted to a receiver in which the coded signals are used to produce an analogue signal corresponding to the complex wave.
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| 58 | Communication system utilizing constant amplitude pulses | US77866347 | 1947-10-08 | US2568721A | 1951-09-25 | DELORAINE EDMOND MAURICE; REEVES ALEC HARLEY |
| 59 | SYSTEMS AND METHODS FOR COMPRESSING A DIGITAL SIGNAL IN A DIGITAL MICROPHONE SYSTEM | EP16183887.5 | 2014-04-08 | EP3166331A1 | 2017-05-10 | Melanson, John, L.; Tucker, John C. |
In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a digital signal (DIGITAL_OUT) having a plurality of quantization levels, wherein the conversion is performed such that each quantization level is represented by one or more transitions or one or more absences of transitions of one or more bits of the digital signal (DIGITAL_OUT).
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| 60 | SYSTEMS AND METHODS FOR COMPRESSING A DIGITAL SIGNAL IN A DIGITAL MICROPHONE SYSTEM | EP14722934.8 | 2014-04-08 | EP2984760A2 | 2016-02-17 | MELANSON, John L.; TUCKER, John C. |
| In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a first digital signal having a plurality (e.g., more than 3) of quantization levels, and in the digital domain, process the first digital signal to compress the first digital signal into a second digital signal having fewer quantization levels (e.g., +1, 0, -1) than that of the first digital signal. | ||||||
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