Method and apparatus for reducing impact of transistor random mismatch in circuits专利检索- 模拟值转换到差分调制或相反转换专利检索查询-专利查询网

Method and apparatus for reducing impact of transistor random mismatch in circuits
申请号	US15482020	申请日	2017-04-07	公开(公告)号	US10097169B1	公开(公告)日	2018-10-09
申请人	Micron Technology, Inc.;			发明人	Dong Pan; John D. Porter;
摘要	An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.
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