子分类：
| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | Modulator with variable quantizer | EP13179842.3 | 2013-08-09 | EP2696657A3 | 2014-06-18 | Tomasovics, Attila; Rabenstein, Arno |
Representative implementations of devices and techniques provide a variable quantizer for a modulator. A compare value of the quantizer changes with each clock cycle of the modulator. The variable compare value results in a spread spectrum output of the modulator.
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| 62 | GLOBAL LOOP INTEGRATING MODULATOR | EP04731306.9 | 2004-05-06 | EP1632024A2 | 2006-03-08 | POULSEN, Soren |
| A switch-mode modulator operating at a two-level voltage and including an alternating output stage (3), an optional output filter (5) and a feedback including a function block (14) with a transfer function (MFB). The modulator furthermore includes a forward block (12) provided with means for calculating the difference between the signal (14a) originating from the function block (14) and a reference signal (REF) as well as with a transfer function (MFW). The output (13) of the forward block (12) is the input of a Schmitt-trigger (9), which generates switch on signals (2) for changing the output stage. The output voltage (VOUT) of the modulator applying either after the optional output filter (5) or the output stage (3) is fed back through the function block (14) so as to generate the signal (14a) fed back. The transfer function of the function block (14) and of the forward block (12) is chosen both in response to the transfer function of the output filter (5) and in response to the desired total open-loop-transfer function of the modulator. | ||||||
| 63 | Electronic sampling circuit | EP98202715.3 | 1998-08-13 | EP0898375A3 | 2002-10-02 | Fuggle, Graham Anthony; Law, Derek; Edwards, Stephen John |
An electronic sampling circuit for determining redox potentials, and consequently specie concentration, in a photographic solution, applies a linear ramp of a square wave voltage to a first electrode (6) immersed in the solution. The current drawn by an adjacent electrode (12) is converted to a voltage for sampling. A pair of sample-and-hold circuits (40,42) store signals sampled at the peak and adjacent trough respectively of a square wave pulse, and a subsequent analogue difference circuit (44) subtracts the two signals. The resulting signal is converted to a digital code by a low cost, low bit count analogue-to-digital converter (46), which is stored on a microprocessor (48). The sampling process is repeated for successive square waves along the ramp. This circuit configuration enables the difference between analogue signals to be measured where the signals differ in amplitude by small amounts but have a wide dynamic range, without the need for an expensive, high bit count analogue-to-digital converter. |
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| 64 | Method and apparatus for producing pulses | EP91117210.4 | 1991-10-09 | EP0540763B1 | 1996-01-10 | Nakanuma, Tadashi |
| 65 | WAVEFORM A/D CONVERTER AND D/A CONVERTER. | EP93913522 | 1993-06-15 | EP0601201A4 | 1995-09-27 | KAWABATA MASAYUKI |
| In order to implement high resolution A/D (or D/A) conversion, the differentiated waveform of an analogue (or digital) waveform signal is generated by a differentiated waveform generating unit (10). The differentiated waveform is cyclically distributed at the timings of clock signals (CK0) to integrators (141 to 14N) (N is an integer of 2 or more). These integrated outputs are converted into digital (or analogue) signals by converters (151 to 15N). These converted outputs are added by an adder (16). The added result is output as a digital (or analogue) waveform signal. | ||||||
| 66 | COMPARATOR, AD CONVERTER, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ROTATION DETECTOR | US15651075 | 2017-07-17 | US20180226961A1 | 2018-08-09 | Hideki SHIMAUCHI; Kanji KITAMURA; Mutsuo DAITO; Akio KAMIMURAI; Masatoshi UCHINO; Yoshinori TATENUMA; Akira KOSHIMIZU |
| Provided is a comparator configured to compare input voltages, which are input to a first dynamic comparator and a second dynamic comparator, with a reference voltage, select either an output signal of the first dynamic comparator or an output signal of the second dynamic comparator based on the comparison result, output the selected output signal, and control clock signals, which are input to the first dynamic comparator and the second dynamic comparator respectively, based on the comparison result, so as to stop the operation of the dynamic comparator of which output signal is not selected. | ||||||
| 67 | MODEM AND RF CHIPS, APPLICATION PROCESSOR INCLUDING THE SAME AND OPERATING METHOD THEREOF | US15614667 | 2017-06-06 | US20180062692A1 | 2018-03-01 | JUN-HO HUH; HO-RANG JANG; SEOK-CHAN KIM; IN-TAE KANG; SANG-HEON LEE; KWAN-YEOB CHAE; JUNE-HEE LEE; SANG-HUNE PARK; JAE-CHOL LEE; HYUNG-KWEON LEE |
| A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal. | ||||||
| 68 | POWER ROUTER APPARATUS FOR GENERATING CODE-MODULATED POWERS | US15270919 | 2016-09-20 | US20170117913A1 | 2017-04-27 | ATSUSHI YAMAMOTO; SHOICHI HARA; TAIKI NISHIMOTO; KOHEI MASUDA |
| A power router apparatus includes: a power divider that divides predetermined power into a plurality of divided powers including first divided power and second divided power; a first code modulator that code-modulates the first divided power with a first modulation code to generate first code-modulated power, which is alternating-current power; and a second code modulator that code-modulates the second divided power with a second modulation code to generate second code-modulated power, which is alternating-current power. | ||||||
| 69 | Systems and methods for reducing non-linearities of a microphone signal | US14247987 | 2014-04-08 | US09571931B1 | 2017-02-14 | John L. Melanson; John C. Tucker |
| To correct for non-linearities in the response of a microphone as a function of sound pressure level incident upon the microphone, a displacement non-linearity function is applied to the signal path of the microphone, wherein the displacement non-linearity function is a function of the digital audio output signal and has a response modeling non-linearities of the displacement as a function of a sound pressure level incident upon the microphone. | ||||||
| 70 | Systems and methods for minimizing noise in an amplifier | US14248054 | 2014-04-08 | US09419562B1 | 2016-08-16 | John L. Melanson; John C. Tucker |
| An amplifier may include a plurality of stages, wherein each stage may have an amplifier stage output configured to generate an amplifier output signal and a transistor coupled at its gate terminal to the amplifier input and to the gate terminals of the transistors of the other amplifier stages. Each stage may be configured to periodically and cyclically operate in an amplifier mode in which the amplifier stage generates at its corresponding amplifier stage output a power-amplified version of a signal received at the amplifier input and a in reset mode in which the transistor of the stage operating in the reset mode has an electrical property thereof reset. At any given time, at least one amplifier stage is operating in the amplifier mode. The amplifier may be configured to output as an output signal one of the amplifier output signals corresponding to an amplifier stage operating in the amplifier mode. | ||||||
| 71 | NOISE SHAPING FOR DIGITAL PULSE-WIDTH MODULATORS | US14691084 | 2015-04-20 | US20150229324A1 | 2015-08-13 | Eric SOENEN; Alan ROTH; Martin KINYUA; Justin SHI; Justin GAITHER |
| A circuit includes an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a digital filter configured to filter the digital output and a noise shaper. The noise shaper is configured to truncate the filtered digital output and generate a noise shaper output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC) configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output. | ||||||
| 72 | Feedforward delta-sigma modulator | US14332396 | 2014-07-16 | US09035814B2 | 2015-05-19 | Che-Wei Chang |
| A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder. | ||||||
| 73 | Noise shaping for digital pulse-width modulators | US13619034 | 2012-09-14 | US09013341B2 | 2015-04-21 | Eric Soenen; Alan Roth; Martin Kinyua; Justin Shi; Justin Gaither |
| A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output. | ||||||
| 74 | FEEDFORWARD DELTA-SIGMA MODULATOR | US14332396 | 2014-07-16 | US20150022387A1 | 2015-01-22 | Che-Wei Chang |
| A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder. | ||||||
| 75 | SYSTEMS AND METHODS FOR GENERATING A DIGITAL OUTPUT SIGNAL IN A DIGITAL MICROPHONE SYSTEM | US14247686 | 2014-04-08 | US20140301571A1 | 2014-10-09 | John L. Melanson; John C. Tucker |
| In accordance with embodiments of the present disclosure, a digital microphone system may include a microphone transducer and a digital processing system. The microphone transducer may be configured to generate an analog input signal indicative of audio sounds incident upon the microphone transducer. The digital processing system may be configured to convert the analog input signal into a first digital signal having three or more quantization levels, and in the digital domain, process the first digital signal to convert the first digital signal into a second digital signal having two quantization levels. | ||||||
| 76 | Noise shaping for digital pulse-width modulators | US12959869 | 2010-12-03 | US08299946B2 | 2012-10-30 | Eric Soenen; Alan Roth; Martin Kinyua; Justin Shi; Justin Gaither |
| A noise shaper that compares an input signal to a feedback output signal, which is a truncated version of the input signal, and generates the difference between the two signals (i.e., the error). The noise shaper then integrates the errors by adding to the error multiple of its delayed versions, and quantizes the integrated errors in such a way that the spectrum of the quantization noise is shaped toward high frequencies to be removed by a LC low-pass filter used in conjunction with the noise shaper. The low frequency content of the desired signal is mostly unaffected. | ||||||
| 77 | Device and methods for biphasic pulse signal coding | US12063099 | 2006-08-08 | US08139654B2 | 2012-03-20 | Du Chen; John G. Harris; Jose C. Principe |
| A method for coding time signals based on generating an asynchronous biphasic pulse train is provided. The method includes generating response signals based upon one or more input signals. A pulse comprises a positive pulse if a voltage of the response signal is greater than a predetermined positive voltage threshold. A pulse comprises a negative pulse if the voltage of the response signal is less than a predetermined negative voltage threshold. The method further includes a method for the reconstruction of a uniformly sampled version of the original signal. | ||||||
| 78 | Method and apparatus for measuring a low power signal | US10956015 | 2004-09-30 | USRE39527E1 | 2007-03-27 | Volker Brombacher; Fritz Bek |
| Low intensity light is incident upon a photodiode whose output is coupled to an integrator. The output of the integrator is coupled to an input of an A/D converter, whose output is coupled to a microprocessor, whose output is coupled to a filter. A second output of the microprocessor is coupled to a gate electrode of a FET to provide a reset signal to the FET to reset the integrator. The microprocessor compares the digital samples of the integrated signal from the A/D converter and, firstly, generates the reset signal if a sample is beyond a set limit, and, secondly, calculates delta values between adjacent samples and interpolates the delta values for the reset periods so as to provide a continuous data stream which can be filtered by a filter matched to the form of the original signal. | ||||||
| 79 | Global loop integrating modulator | US10556210 | 2004-05-06 | US20060261885A1 | 2006-11-23 | Soren Poulsen |
| A switch-mode modulator operating at a two-level voltage and including an alternating output stage (3), an optional output filter (5) and a feedback including a function block (14) with a transfer function (MFB). The modulator furthermore includes a forward block (12) provided with means for calculating the difference between the signal (14a) originating from the function block (14) and a reference signal (REF) as well as with a transfer function (MFW). The output (13) of the forward block (12) is the input of a Schmitt-trigger (9), which generates switch on signals (2) for changing the output stage. The output voltage (VOUT) of the modulator applying either after the optional output filter (5) or the output stage (3) is fed back through the function block (14) so as to generate the signal (14a) fed back. The transfer function of the function block (14) and of the forward block (12) is chosen both in response to the transfer function of the output filter (5) and in response to the desired total open-loop-transfer function of the modulator. | ||||||
| 80 | Method and apparatus for measuring a low power signal | US10095235 | 2002-03-11 | US06660991B2 | 2003-12-09 | Volker Brombacher; Fritz Bek |
| Low intensity light is incident upon a photodiode whose output is coupled to an integrator. The output of the integrator is coupled to an input of an A/D converter, whose output is coupled to a microprocessor, whose output is coupled to a filter. A second output of the microprocessor is coupled to a gate electrode of a FET to provide a reset signal to the FET to reset the integrator. The microprocessor compares the digital samples of the integrated signal from the A/D converter and, firstly, generates the reset signal if a sample is beyond a set limit, and, secondly, calculates delta values between adjacent samples and interpolates the delta values for the reset periods so as to provide a continuous data stream which can be filtered by a filter matched to the form of the original signal. | ||||||
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