Dynamic offset cancellation in sigma-delta converter |
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申请号 | US14811311 | 申请日 | 2015-07-28 | 公开(公告)号 | US09385746B1 | 公开(公告)日 | 2016-07-05 |
申请人 | Avago Technologies General IP (Singapore) Pte. Ltd.; | 发明人 | Gek Yong Ng; Qian Tao; | ||||
摘要 | A sigma-delta converter, analog-to-digital conversion system, and an Integrated Circuit (IC) chip are disclosed that include a main sigma-delta modulator and an auxiliary sigma-delta modulator. The auxiliary sigma-delta modulator is electrically matched with the main sigma-delta modulator and is configured to generate an output that is incorporated into a feedback loop of the main sigma-delta modulator to enable the main sigma-delta modulator to adjust an offset signal applied at a main analog channel. | ||||||
权利要求 | What is claimed is: |
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说明书全文 | The present disclosure is generally directed toward an analog-to-digital converter and, in particular, sigma-delta converters. Industrial and automotive applications such as motor current sensing and battery voltage monitoring require precise measurement of the current or voltage level. Offset voltage present in a sensor chip used for precision current or voltage measurement will appear in the measurement reading and hence requires one-time calibration at the system level to remove this offset from the measurement. Offset voltage of a sensor chip is defined as the output voltage when the input signal is zero, in other words the condition when the input signal is connected to ground. One-time offset calibration is performed by first connecting the input of the sensor chip to ground to measure the offset voltage at the output, and then subtracting this offset voltage from subsequent readings when the sensor is in normal operation. For practical reasons, calibration is performed only one time at nominal operating conditions. Hence, only a fixed offset is eliminated and so this scheme is only accurate for measurement done at the calibration conditions. As offset changes over the device operating conditions such as temperature and supply voltage, and also varies from part to part due to manufacturing process shift, this calibration scheme is not effective to cancel offset due to drifts in operating environment. This calibration has to be performed for every sensor chip at the system level The present disclosure is described in conjunction with the appended figures, which are not necessarily drawn to scale: The ensuing description provides embodiments only, and is not intended to limit the scope, applicability, or configuration of the claims. Rather, the ensuing description will provide those skilled in the art with an enabling description for implementing the described embodiments. It being understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the appended claims. Various aspects of the present disclosure will be described herein with reference to drawings that are schematic illustrations of idealized configurations. As such, variations from the shapes of the illustrations as a result, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the various aspects of the present disclosure presented throughout this document should not be construed as limited to the particular circuit elements illustrated and described herein but are to include deviations in circuits and functionally-equivalent circuit components. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The term “and/or” includes any and all combinations of one or more of the associated listed items. While embodiments of the present disclosure will be described in connection with a sigma-delta modulator, it should be appreciated that embodiments of the present disclosure are not so limited. In particular, the concepts described herein can be used for any type of analog-to-digital converter or converters or similar circuit configurations operating in a mixed signal (e.g., analog and digital) environment. While the particular type of low-level circuit described herein (e.g., a Serializer/Deserializer (SerDes)) is capable of utilizing the sigma-delta modulator system and method, other types of receivers or mixed signal communication system components can also benefit from the concepts described herein. Any type of Integrated Circuit (IC), IC chip, IC chip component, radar, audio/video signal processing, telephone system, etc. can utilize the sigma-delta modulator systems and methods described herein. Accordingly, a sigma-delta modulator is disclosed herein. It is one aspect of the present disclosure to provide an offset calibration method and system for implementing said method in a feedback system on-chip as part of main sensor (e.g., voltage or current sensor) circuitry. In some embodiments, a dynamic calibration loop is used as it is always active and so the offset calibration is always effective over the entire device operating conditions. As the calibration loop experiences the same environment as the main sensor circuitry, the calibration loop eliminates not only the fixed offset but also offset drifts over the entire device operating conditions. As the calibration is within the sensor chip, there is no extra calibration effort at the system level and the measurement is always accurate and free of offset. In some embodiments, an offset calibration loop is described that an auxiliary input branch coupled and matched electrically to the main sigma-delta converter/modulator, with the auxiliary input branch storing the offset of the main converter digitally, and then feeding this offset value back to the main converter through negative feedback, thus eliminating offset from the digital output of the main converter dynamically. It should be appreciated that the offset calibration loop and the auxiliary input branch for the offset calibration loop may be implemented in a number of different ways, some of which are depicted and described herein. Those of ordinary skill in the art will understand that any type of offset calibration loop can be used without departing from the scope of the present disclosure. Referring now to The analog-to-digital converter circuit 108 may include any type or collection of circuit components that are capable of converting the analog input signal received from the analog input circuit 104 into a digital signal. The digital signal can then be provided to the digital circuit 112 or multiple digital circuits 112 for processing with digital circuit components (e.g., logic circuits components, transistors, logic gates, logic switches, latches, etc.). The digital circuit 112 may be embodied as an IC on a single or multiple IC chips. With reference now to The circuit 200 is shown to include a voltage input Vin, a reference voltage Vref, and a measured output Dout. The circuit 200 is also shown to include a summing node 208, a loop filter 212, a quantizer 216, and a feedback loop in which a digital-to-analog converter (DAC) 220 is situated. The voltage input Vin may alternatively correspond to a current input Iin without departing from the scope of the present disclosure. The voltage input Vin may correspond to the analog input signal to be measured by the circuit 200. The reference voltage Vref may correspond to an analog input reference signal, for example ground or some other reference signal. The voltage input Vin and negative loop feedback of the DAC 220 are provided as inputs to the summing node 208 to determine an error voltage Ve. The error voltage Ve is provided to the loop filter 212, which may filter one or more frequencies or frequency bands of interest out of the error voltage Ve. The loop filter 212 provides its output to the quantizer 216 that generates the measured output Dout. In some embodiments, the measured output Dout corresponds to a digital output signal that is in the form of a bitstream of ‘1's’ and ‘0's’ with a pulse density, D, that represents the voltage input Vin as a ratio of the reference voltage Vref. In the depicted embodiments, the circuit 200 is configured as a sigma-delta modulator or sigma-delta converter 204 (the terms may be used interchangeably). The sigma-delta modulator 204 is capable of producing a digital representation of the measured output Dout. In a steady state, the negative feedback loop containing the DAC 220 will make the error voltage Ve approximately zero, which essentially causes the voltage input Vin to equal the ratio of the reference voltage Vref times the measured output Dout. In other words, the error voltage Ve can be expressed as the following: Ve=Vin*(Dout*Vref) When the error voltage Ve is approximately equal to zero, then the voltage input Vin can be expressed as the following: Vin=Dout*Vref In an ideal system without offset, when the voltage input Vin equals zero, then the measured output Dout will also equal zero, which means that the measured output Dout is offset-free. With reference now to When the voltage input Vin is zero, and the offset voltage Vos is not zero, then the measured output Dout will also not be zero, which means that the measured output Dout has an offset component. In particular, the measured output Dout can be expressed as the following where Dz is the offset-free pulse density representing the voltage input Vin and Dos is the pulse density representing the offset voltage Vos: D=Dz+Dos As can be appreciated, while adding a static offset at the input or subtracting a static offset from the output in the calibration process does solve some problems associated with the inherent offset of a circuit, there are still issues associated with using a static offset. In particular, the static offset does not compensate for dynamic changes in the circuit due to temperature conditions, voltage conditions, process variations, and/or noise. Thus, additional measures need to be taken. With reference to In the depicted embodiment, the auxiliary sigma-delta modulator 404 comprises the offset voltage Vos and the reference voltage Vref as its input. The auxiliary sigma-delta modulator 404 generates auxiliary output Dos, which is the pulse density representing the offset voltage Vos. The auxiliary output Dos is added to the main sigma-delta modulator 204 in a negative feedback loop, thereby resulting in the removal of the offset from the main sigma-delta modulator output Dz. Since the auxiliary sigma-delta modulator 404 is electrically matched to the main sigma-delta modulator 204, the offset voltage Vos can be emulated simply by connecting its inputs to ground. With reference now to By using the feedback mechanism depicted in With reference now to In some embodiments, this additional path between the second DAC 604 and the summing node 208 acts like a second input to the main sigma-delta modulator 204, with its input containing the equivalent offset of the main sigma-delta modulator 204, resulting in zero offset in the final output Dz. This particular implementation may be easier to implement than the first method depicted in One possible detailed implementation of the circuit 600 is shown in a detailed circuit diagram 700 depicted in The reference resistor Rref and input resistor Rin may have their outputs connected to a common node, that is feed to an input of an amplifier 704. The amplifier 704 may have a capacitor Cint connected in parallel thereto, thereby enabling the amplifier 704 and capacitor Cint to collectively operate as filter 212. The output of the amplifier 704 is provided to a quantizer 708, which is an example of quantizer 216. The quantizer 708 is shown to output a pair of quantized/digital outputs Qz and Qzbar, which are used to control the two switches SWp and SWn. The second DAC 604 is shown to include a reference resistor Rref, which may be similar or identical in resistance with the reference resistor Rref in the main sigma-delta modulator 204. In other words, the same reference resistor Rref is used because the auxiliary sigma-delta modulator 404 is electrically matched with the main sigma-delta modulator 204. With reference now to With reference now to In some embodiments, the auxiliary second-order sigma-delta modulator 1012 is a duplication of the main sigma-delta modulator 1004. This duplication effectively enables the auxiliary second-order sigma-delta modulator 1012 to function as an electrical equivalent of the main second-order sigma-delta modulator 1004. By having this electrical equivalency, the offset cancellation generated by the auxiliary second-order sigma-delta modulator 1012 is capable of properly cancelling out the offset experienced by the main second-order sigma-delta modulator 1004. In simulation of circuit 1000, the offset cancellation is achieved using the auxiliary second-order sigma-delta modulator 1012 as the auxiliary bitsteam generator. The noise floor is not disturbed, and the signal to noise ratio for the circuit 1000 is effectively the same as an ideal/offset-free case. With reference now to In simulation of circuit 1100, the offset cancellation is achieved using the auxiliary first-order sigma-delta modulator 1112 as the auxiliary bitstream generator. As with circuit 1000, the noise floor when implementing circuit 1100 is not disturbed, and the signal to noise ratio of the circuit 1100 is effectively the same as an ideal/offset-free scenario. With reference now to With reference now to Specific details were given in the description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments. While illustrative embodiments of the disclosure have been described in detail herein, it is to be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be construed to include such variations, except as limited by the prior art. |