| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | 携带同步编码的信息和帧定时同步的方法 | CN200680038917.4 | 2006-09-25 | CN101297486B | 2010-05-19 | 弗雷迪克·伯格恩 |
| 本发明公开了一种通信系统中传送数据和同步信息的改进方法。该方法利用一种增加了重复结构的循环可交换码来携带数据和同步信息。接收机在解码过程中利用该码的这种重复结构来降低复杂度，包括：用假设Hx估测接收到码字的重复码字结构，并选择该重复码字结构对应的假设；接收机在解码过程中根据所选择的假设进行码字元素的分集合并；通过将分集合并后的码字元素与满足假设的所有可能的码字进行比较来进一步检测出接收到的码字。 | ||||||
| 22 | 信息块编码及同步检测的方法和装置 | CN200710106648.7 | 2007-05-26 | CN101312349A | 2008-11-26 | 耿东玉; 封东宁; 梁伟光; 弗兰克·埃芬博格 |
| 本发明涉及通信领域，公开了一种信息块编码及同步检测的方法和装置。本发明中，根据满足特定条件的同步字符序列进行信息块编码和同步检测，可以在不增加复杂度的前提下，有效地降低错误同步的概率。本发明还提出了在不同的长度下最优的同步字符序列，进一步降低了错误同步的概率。 | ||||||
| 23 | 携带同步编码的信息和帧定时同步的方法 | CN200680038917.4 | 2006-09-25 | CN101297486A | 2008-10-29 | 弗雷迪克·伯格恩 |
| 本发明公开了一种通信系统中传送数据和同步信息的改进方法。该方法利用一种增加了重复结构的循环可交换码来携带数据和同步信息。接收机在解码过程中利用该码的这种重复结构来降低复杂度，包括：用假设Hx估测接收到码字的重复码字结构，并选择该重复码字结构对应的假设；接收机在解码过程中根据所选择的假设进行码字元素的分集合并；通过将分集合并后的码字元素与满足假设的所有可能的码字进行比较来进一步检测出接收到的码字。 | ||||||
| 24 | 数据传输方法、块同步信号检测方法、以及再现装置 | CN02802625.X | 2002-07-09 | CN1284170C | 2006-11-08 | 伊藤明; 广瀬俊彦 |
| 一种用于检测块同步信号的方法，它可以从代码序列中区分出同步信号，当再现或接收数据时可以检测由代码字组成的块的第一部分。向同步字检测器(10)提供从介质(1)再现的再现信号中包含的同步字和代表ID信息的时期的窗信号sync_window(同步窗)，同步字检测器(10)通过使用窗信号Sync_window，从PRML维特比检测器(6)检测到的位串中检测同步字，其中所述窗信号Sync_window是根据从奇偶校验电路(12)提供的奇偶性OK信号产生。 | ||||||
| 25 | 数据传输方法、块同步信号检测方法、以及再现装置 | CN02802625.X | 2002-07-09 | CN1465064A | 2003-12-31 | 伊藤明; 广濑俊彦 |
| 一种用于检测块同步信号的方法，它可以从代码序列中区分出同步信号，当再现或接收数据时可以检测由代码字组成的块的第一部分。向同步字检测器(10)提供从介质(1)再现的再现信号中包含的同步字和代表ID信息的时期的窗信号sync_window(同步窗)，同步字检测器(10)通过使用窗信号Sync_window，从PRML维特比检测器(6)检测到的位串中检测同步字，其中所述窗信号Sync_window是根据从奇偶校验电路(12)提供的奇偶性OK信号产生。 | ||||||
| 26 | 用误码率的数字图像记录和再现设备的跟踪控制电路和方法 | CN97110074.8 | 1997-04-11 | CN1128445C | 2003-11-19 | 李宇年; 李炯周 |
| 一种数字图像记录和再现设备的跟踪控制电路，该设备具有根据伺服控制信号控制在磁记录介质上的记录操作的一个机构和一个ECC电路，并通过同步数据块再现记录在所述记录介质上的数据，所述跟踪控制电路包括：一个误码率检测器，用于计算来自所述ECC电路的误差标记的频率，和产生一个误码率数据；一个控制单元，用于在来自所述误码率检测器的误码率数据超过一个预定极限处产生与所述误码率数据相对应的跟踪控制数据；和一个伺服电路。 | ||||||
| 27 | 编码率的检测方法以及编码率的检测装置 | CN00804366.3 | 2000-06-27 | CN1342345A | 2002-03-27 | 掛水隆史; 镰田刚弘; 中居祐二 |
| 一种编码率检测方法,用于对所接收的编码信号的给定编码率进行检测。利用具有与第一编码率对应的频率的第一同步信号,对编码信号进行译码,并生成第一译码信号(ST11),判断第一译码信号是否取得了同步(ST12)。当不能取得同步时,只生成具有与第一编码率的差值小于由下限值以及上限值所决定的编码率的容许值的第二编码率所对应的频率的第二同步信号(ST13、ST17)。 | ||||||
| 28 | 用于检测维特比译码器中同步的方法和电路 | CN93119980.8 | 1993-12-24 | CN1093844A | 1994-10-19 | 轰俊哉 |
| 用于校验由维特比译码器在维特比译码处理中确定的最大路径尺度状态已经转换定的之前的状态，使用最大路径尺度状态，并确定转换之间转换移值的转移值输出电路。一个用于确定转移值和软判断接收数据之间在每个间隔中的相关性并输出表示每个间隔中相关性的相关值的相关器。一个根据每个间隔中的转移值确定接收的数据是否处在同步或非同步状态的同步/非同步判定电路。 | ||||||
| 29 | DATA LINE STORAGE AND TRANSMISSION UTILIZING BOTH ERROR CORRECTING CODE AND SYNCHRONIZATION INFORMATION | PCT/US2010056145 | 2010-11-10 | WO2011071649A3 | 2011-09-29 | AGARWAL RAJAT; HUDDLESTON C SCOTT |
| Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted. | ||||||
| 30 | APPARATUS AND METHOD FOR SYNCHRONIZATION OF TRELLIS STATES IN A NETWORK | PCT/US2010048748 | 2010-09-14 | WO2011034844A2 | 2011-03-24 | BOUILLET AARON REEL; BELOTSERKOVSKY MAXIM; PASCAL GRAVOILLE |
| Communications systems often use networks including separately located transmitters and exciters for signal transmission. An apparatus and method for synchronization of trellis states in a network are provided. The apparatus and method provide for generating a data stream including at least one training sequence (402), generating trellis initialization information based on the data stream (404), inserting the trellis initialization information into the data stream in a predetermined location (406). The present disclosure further provides for inserting in the data stream a packet for determining when to perform a trellis state reset. In certain embodiments, the packet includes a bit for determining when to selectively disable parity replacement of the data stream to synchronize trellis states across multiple exciters. | ||||||
| 31 | INCREMENTAL REDUNDANCY TRANSMISSION IN A MIMO COMMUNICATION SYSTEM | PCT/US2004029648 | 2004-09-09 | WO2005025117A3 | 2007-03-29 | KADOUS TAMER |
| An incremental redundancy (IR) transmission in a MIMO system (Fig. 1), a transmitter 110 processes a data packet based on a selected rate to obtain multiple data symbol blocks. The transmitter transmits one data symbol block at a time until a receiver correctly recovers the data packet or all blocks are transmitted. Whenever a data symbol block is received from the transmitter, the receiver 150 detects a received symbol block to obtain a detected symbol block, processes all detected symbol blocks obtained for the data packet, and provides a decoded packet. If the decoded packet is in error, then the receiver repeats the processing when another data symbol block is received for the data packet. The receiver may also perform iterative detection and decoding on the received symbol blocks for the data packet multiple times to obtain the decoded packet. | ||||||
| 32 | Incremental redundancy transmission in Mimo communication system | JP2010128926 | 2010-06-04 | JP5280404B2 | 2013-09-04 | タマー・カドウス |
| For an incremental redundancy (IR) transmission in a MIMO system, a transmitter processes (e.g., encodes, partitions, interleaves, and modulates) a data packet based on a selected rate to obtain multiple data symbol blocks. The transmitter transmits one data symbol block at a time until a receiver correctly recovers the data packet or all blocks are transmitted. Whenever a data symbol block is received from the transmitter, the receiver detects a received symbol block to obtain a detected symbol block, processes (e.g., demodulates, deinterleaves, re-assembles, and decodes) all detected symbol blocks obtained for the data packet, and provides a decoded packet. If the decoded packet is in error, then the receiver repeats the processing when another data symbol block is received for the data packet. The receiver may also perform iterative detection and decoding on the received symbol blocks for the data packet multiple times to obtain the decoded packet. | ||||||
| 33 | Synchronization code recovery circuit and method | JP2003044636 | 2003-02-21 | JP4439826B2 | 2010-03-24 | 仲 彦 徐; 泳 姙 朱; 胤 雨 李; 相 鉉 柳; 声 休 韓; 盛 ▲ひ▼ 黄 |
| 34 | Data writing device and storage system | JP2005276921 | 2005-09-22 | JP2007087534A | 2007-04-05 | ESUMI ATSUSHI; MIZUNO SHIYUUDO |
| PROBLEM TO BE SOLVED: To align data for error correction encoding and parity data without handshaking while writing the data and the parity data at high speed in a storage device. SOLUTION: An LDPC encoding part 304 comprises: a timing control circuit 326 for controlling the timing of body data and outputting the timing-controlled body data to a writing circuit 334; a parity generation circuit 328 for generating parity data by performing the LDPC encoding of an input signal series and outputting the parity data to the writing circuit 334; and the writing circuit 334 for successively receiving the body data and the parity data and outputting the received data to the storage device through a write precompensation part 305, a driver 306, etc. COPYRIGHT: (C)2007,JPO&INPIT | ||||||
| 35 | Synchronization code recovery circuit and method | JP2003044636 | 2003-02-21 | JP2003319345A | 2003-11-07 | HAN SUNG-HYU; LEE YOON-WOO; SEO JOONG-EON; JU YOUNG-IM; RYU SANG-HYUN; HWANG SUNG-HEE |
| <P>PROBLEM TO BE SOLVED: To provide a synchronization code recovery circuit and method capable of recovering a defective synchronization code to an accurate location so as to furthermore enhance the reliability of data. <P>SOLUTION: The synchronization code recovery circuit and method compares an original synchronization pattern with a pattern of a next synchronization candidate recovered at a plurality of synchronization locations when no synchronization code is detected from a received bit stream, produces location information at which the most proper synchronization pattern is obtained on the basis of a result of comparison, and recovers the synchronization code at a location corresponding to the location information. Further, the synchronization code recovery circuit and method of this invention applies error correction to the next synchronization candidate recovered at a plurality of synchronization locations, generates the most proper location information of the succeeding synchronization pattern on the basis of the result of error correction and recovers the synchronization code at a location corresponding to the location information when no synchronization code is detected from the received bit stream. <P>COPYRIGHT: (C)2004,JPO | ||||||
| 36 | Method and apparatus for communication of interleaved data | JP21691193 | 1993-08-10 | JP3402680B2 | 2003-05-06 | ウー・エイチ・ペイク; ジョン・エム・フォックス; スコット・エー・レリー |
| 37 | Data transmission method, block synchronizing signal detecting method and reproducing device | JP2001208496 | 2001-07-09 | JP2003022617A | 2003-01-24 | ITO AKIRA; HIROSE TOSHIHIKO |
| PROBLEM TO BE SOLVED: To make discriminable between a synchronizing signal and a code sequence and to make surely recognizable the top of a block composed of a plurality of code words in reproducing or receiving of data. SOLUTION: Synchronous words are detected by using the window signal Sync- window from in accordance with parity OK signal supplied from a parity check circuit 12 relating to the bit string detected in a PRML Viterbi detector 36 by a synchronous word detector 8 to which the window signal Sync- window indicating the period of the synchronous word and ID information included in the regenerative signal regenerated from media 14 is supplied. | ||||||
| 38 | Data receiver | JP28563597 | 1997-10-17 | JP3344934B2 | 2002-11-18 | 敏久 中井; 靖子 松村; 茂 福永 |
| 39 | Code rate detecting method and coding rate detecting device | JP18282999 | 1999-06-29 | JP3340403B2 | 2002-11-05 | 祐二 中居; 隆史 掛水; 剛弘 鎌田 |
| 40 | Synchronous / asynchronous determine the method and apparatus of the Viterbi decoding signal | JP16874497 | 1997-06-25 | JP3155728B2 | 2001-04-16 | ジョン ソプ ベク |
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