Codec |
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| 申请号 | EP93103244.5 | 申请日 | 1993-03-01 | 公开(公告)号 | EP0559123A3 | 公开(公告)日 | 1993-10-20 |
| 申请人 | Oki Electric Industry Co., Ltd.; | 发明人 | Okamoto, Seiji, c/o Oki Elec. Ind. Co., Ltd.; | ||||
| 摘要 | In a codec having a coding section A/D converting an analog signal into a digital signal, and a decoding section D/A converting a received digital signal into an analog signal, a decoding timing generating circuit (50) is provided to generate a D/A conversion timing signal (S50) on the basis of a clock signal (S30b) generated by a coding PLL circuit (30) and a reading completion signal (S61a) supplied from decoding controller (61). In synchronism with this signal (S50), a D/A converter 62 converts the digital signal Di read by the decoding controller 61, into an analog signal, and sends it to the decoding filter 63. The decoding filter (63) operates synchronism with the clock signal (S30b) generated by the coding PLL circuit (30) to filter the output of the D/A converter (62), and outputs it as the analog signal (Ao). The S/N ratio due to asynchronous noises is improved, and the size, complexity, and the power consumption of the overall circuit are reduced, so the codec is suitable for implementation in an integrated circuit. | ||||||
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