METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)专利检索- .模拟/数字/模拟的转换专利检索查询-专利查询网

METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS)
申请号	US15711177	申请日	2017-09-21	公开(公告)号	US20180013442A1	公开(公告)日	2018-01-11
申请人	Maxlinear, Inc.;			发明人	Eric Fogleman; Sheng Ye; Xuefeng Chen; Kok Lim Chan;
摘要	An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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