| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | Multiplexing of the additional bit stream and the first bit stream | JP2003573813 | 2003-02-27 | JP4335695B2 | 2009-09-30 | ペサヴェント ゲイリー; クオ ジャーチェン |
| 42 | Digital signal processing apparatus and reproducing apparatus | JP31622898 | 1998-11-06 | JP4238394B2 | 2009-03-18 | 康彰 関井 |
| 43 | How to adjust the output impedance of the output driver circuit variable | JP2002218315 | 2002-07-26 | JP4008776B2 | 2007-11-14 | ガイ・ハーラン・ハンフリー |
| 44 | Method for variably adjusting output impedance of output driver circuit | JP2002218315 | 2002-07-26 | JP2003069416A | 2003-03-07 | HUMPHREY GUY HARLAN |
| PROBLEM TO BE SOLVED: To provide an output driver circuit that has a higher output impedance rage with a fewer control lines while preventing occurrence of a spike with the output impedance on the signal pad. SOLUTION: A binary weighted thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit. The driver circuit includes an impedance network comprising a plurality of resistive devices each programmably electrically connectable in parallel between a first voltage source and the signal pad. The resistive devices are partitioned into a plurality of sets. A first set of the resistive devices may be programmed in a binary incremental manner to electrically connect one or more of the resistive devices in the first set between the first voltage source and the signal pad. Only if all of the resistive devices in the first set are activated may a second set of the resistive devices be started. Additional sets of the resistive devices may be likewise programmed. COPYRIGHT: (C)2003,JPO | ||||||
| 45 | Digital signal processor and reproducing device | JP31622898 | 1998-11-06 | JP2000149424A | 2000-05-30 | SEKII YASUAKI |
| PROBLEM TO BE SOLVED: To avoid such a situation as an output multi-bit digital signal is fixed at a full-bit (a maximum value) even if a one-bit signal exceeding a maximum modulation factor is inputted when a converter is constituted, which samples down the one-bit signal by using a decimation filter with the specified maximum modulation factor and converts the signal into the multi-bit signal and to attain an average level rising. SOLUTION: A converting part 7 converts a one-bit digital signal D1 from a reproducing signal processing part 4 into a multi-bit digital signal DM and attenuates it. A level detecting part 10 detects the level of the multi-bit digital signal DM converted by the converting part 7. A level control part 12 controls the level of the multi-bit digital signal DM outputted from the converting part 7 not to exceed a full bit according to the level detected by the level detecting part 10. COPYRIGHT: (C)2000,JPO | ||||||
| 46 | Semiconductor memory | JP861892 | 1992-01-21 | JPH0546361A | 1993-02-26 | MACHIDA HIROHISA |
| PURPOSE:To provide the semiconductor storage device which eliminates the increase of an execution time generated by a conversion from redundant binary number data to general binary number data, and can execute an arithmetic processing at a high speed. CONSTITUTION:This semiconductor memory includes plural memory circuits 10, and each of the memory circuits 10 includes a data bit memory cell 11, a sine bit memory cell 12, a converting circuit 13 and a selecting circuit 14. The data bit memory cell 11 stores one bit of regular binary number data or a data bit of one digit of redundant binary number data. The sine bit memory cell 12 stores a sine bit of one digit of the redundant binary number data. The converting circuit 13 converts the redundant binary number data to the general binary number data, based on the data bit stored in the data bit memory cell and the sine bit stored in the sine bit memory cell 12. The selecting circuit 14 selects the data bit stored in the data bit memory cell 11 or one bit of the general binary number data outputted by the converting circuit 13. | ||||||
| 47 | 様々な数値フォーマットのデータを用いてデータに基づく関数モデルを計算するためのモデル計算ユニット、および制御装置 | JP2014135962 | 2014-07-01 | JP2015015026A | 2015-01-22 | FISHER WOLFGANG; NICO BANNOW; ANDRE GUNTORO |
| 【課題】モデル計算ユニット、およびモデル計算ユニットを備えた制御装置を提供する。【解決手段】本発明は、データに基づく関数モデルのためのアルゴリズムを純粋にハードウェア上で計算をするよう構成された演算コア(31)であって、データに基づく関数モデルは、計算データ、特にハイパーパラメータおよびサンプルポイントデータの提供を受けて計算される、上記演算コア(31)と、演算コア(35)に、計算データの少なくとも一部、特に提供されたサンプルポイントデータを所定の数値フォーマットで提供するよう構成された純粋にハードウェアによる変換ユニット(35)と、を備えた、制御装置(1)内でデータに基づく関数モデル、特にガウス過程モデルを計算するモデル計算ユニット(3)に関する。【選択図】図2 | ||||||
| 48 | Modulation coding and decoding method of a bit stream, apparatus, and system (modulation coding and decoding) | JP2010531613 | 2008-10-23 | JP5031100B2 | 2012-09-19 | ミッテルホルツァ、トーマス |
| 49 | Involving conversion between qB / rB and xB / yB encoded bit stream, multiplexing the primary bit stream of the additional bit stream | JP2006518880 | 2004-07-07 | JP2007529146A | 2007-10-18 | ペサヴェント ゲイリー; クオ ジャーチェン |
| 一次ビットストリームの管理は、ｑＢ／ｒＢ符号化ビットストリームをｘＢ／ｙＢ符号化ビットストリームに変換すること、および追加ビットストリームをリンクの送信側でｘＢ／ｙＢ符号化ビットストリームと多重化することを伴う。 追加ビットストリームは次に、ｘＢ／ｙＢ符号化ビットストリームから多重分離化され、ｘＢ／ｙＢ符号化ビットストリームはリンクの受信側でｑＢ／ｒＢ符号化ビットストリームに戻す変換を受ける。 ｘＢ／ｙＢ多重化システムと互換可能な多重化／多重分離化システムを使用して、追加ビットストリームがｑＢ／ｒＢ符号化ビットストリームと多重化されることができるように、ｑＢ／ｒＢ符号化ビットストリームは、ｘＢ／ｙＢ符号化ビットストリームからおよびそれへ、変換される。 ある用途においては、４Ｂ／５Ｂ符号化ビットストリームが８Ｂ／１０Ｂ符号化ビットストリームに変換され、追加ビットストリームはコード−ワードの操作を使用して、８Ｂ／１０Ｂ符号化ビットストリームの１０Ｂコード−ワードと多重化される。
|
||||||
| 50 | Low voltage amplitude signal encoding method and apparatus | JP2006520946 | 2004-07-12 | JP2006528449A | 2006-12-14 | ホセ、デ．ホタ．ピネダ、デ、ギベス; ロヒーニ、クリシュナン |
| バス上で送信されるべき現在の値がバスの前の状態と比較される、相互接続バスを交差するように信号を送信するための符号化小振幅方式。 ビット反転の数がＮよりも多いとき、Ｎはバスの幅であり、反転された信号値を送信するための決定がなされる。 さらに、バス値が反転されているか否かを示すために受信機に「反転」信号も送られる。 次いで、これらの符号化された値は小振幅値に変換され、送信される。 このようにして、相互接続で消費されるエネルギーが最小限であることを保証することができる。 この方策は相互接続での遷移の確率を減少させるだけでなく、従来技術に比べて非常に大きなエネルギー減少を達成するように小振幅値だけを送信する。 | ||||||
| 51 | Time stamping system | JP29345598 | 1998-10-15 | JPH11191168A | 1999-07-13 | RUST ROBERT A |
| PROBLEM TO BE SOLVED: To reduce the size of a memory map by reading respective time stamps, individually determining whether or not respective time stamps are advanced, and individually advancing the respective time stamps in response to the decision means. SOLUTION: This system waits for an update cycle to start (step 5) and updates respective time stamps after a timer for an update cycle ends. Random numbers are generated for the respective time stamps (step 10) and then the time stamps are read out of their locations in the memory (step 20). To advance time stamps, a minimum run length of 0's of the random numbers is determine by using an index table and after the random numbers are compared with the index table (step 30), it is determined whether or not the time stamps are advanced (step 40). When the random numbers match the minimum number of 0's being advanced, the time stamp is advanced. COPYRIGHT: (C)1999,JPO | ||||||
| 52 | Vector quantization method and decoder thereof | JP24412894 | 1994-10-07 | JPH08110799A | 1996-04-30 | IKEDO JIYOUTAROU; KATAOKA AKITOSHI |
| PURPOSE: To hardly generate a large distortion even when a transmission line error occurs. CONSTITUTION: Representative vectors z1i , z2j are selected from code tables 1, 2 respectively, multipliers 21, 22 multiply them by weighting factors w1 , w2 , a synthesis section vector-synthesizes the multiplied vectors z1i w1 , z2j w2 , and a controller 6 selects the combination of z1i , z2j to minimize the distance (distortion) between the synthetic vector yi ,j and the input vector (x). The weighting factors W1 , W2 have the same number of elements as the element number of the vector z1i , and the weighting factors w1 , w2 are selected so that the sum of both diagonal matrixes of the w1 , w2 becomes the constant times the unit matrix when the weighting factor matrixes contain these elements as diagonal elements. | ||||||
| 53 | Multiple resonance type tunneling circuit for positive digit range-4 base-2 to binary conversion | JP14524694 | 1994-05-24 | JPH07147536A | 1995-06-06 | ARUBAATO EICHI TADEIKEN |
| PURPOSE: To constitute a multilevel logic circuit by using a multi-peak type resonance tunneling device by making the binary work of an L-value show the same numeric value as that of a range N when that of the range N is impressed at the input terminal of a voltage divider. CONSTITUTION: The input of a positive digit range-4 base-2 to binary converter is the word S of a range-4 and base-2 which is a positive number and the word S is composed of numbers S0 -S4 (S0 : the least significant digit). The digits are decomposed by means of range-4 base-2 to binary converters 50. The output of each converter 50 is composed of a two-digit binary word and the word has the same value as that of an inputted multilevel digit (where, a carry digit C is the most significant binary digit and W is the least significant digit). An adding circuit 52 generates the digit in an intermediate area 3 by adding the outputs C and W from adjacent converters 50 to each other and the digit is decomposed by means of another converter 50. A decomposing stage 53 generates a word of a range-4 and base-2 of W-1 digit width and a binary bit to the word which is the digit width of the W. | ||||||
| 54 | Binary coding method and increasing/decreasing method with nearly uniform rate of change with respect to binary element | JP31303191 | 1991-11-02 | JPH06120839A | 1994-04-28 | JIYATSUKU BURUJIE; MAAKU JIROORU |
| PURPOSE: To provide a binary coding method for digital data that produces a uniform or an almost uniform mean change rate and to produce a minimum number, that is, a number equal to or close to 1 with respect to a change in a binary element. CONSTITUTION: The coding is conducted in three stages, a value is coded in a 1st reference field 11, the value is coded in a replacement field 12, and finally the replacement field is rotated (23). The procedure begins with a Euclid division 21 for a total number N by a number nR, for each value coded in the replacement field. Two values Q, R are obtained corresponding to the quotient and the residue of the division. The value R is coded by a coding module 22 according to a selected coding logic. The binary series obtained in this way is rotated (23), and the magnitude of the rotation is a function of the value Q. The binary series obtained after the rotation is assigned to the replacement field 12. COPYRIGHT: (C)1994,JPO | ||||||
| 55 | D/a converting circuit | JP11326289 | 1989-05-02 | JPH02292916A | 1990-12-04 | KIMURA SHIGENOBU |
| PURPOSE: To perform the converting operation of good linearity by providing a means which inputs a digital signal, a means which converts a pulse wave, a buffer means, and a means which outputs the output of this buffer means through a low pass filter. CONSTITUTION: The digital signal is inputted to an oversampling digital filter 11 and is subjected to interpolating operation to become data required for a noise shaping circuit 21 of the succeeding stage and is outputted as data X. Data X is converted to a PDM signal by the circuit 21 and is outputted as a quantized signal Y, and the signal Y is supplied to an LPF 32 through an optical coupling circuit 31. Since the input and the output of the circuit 31 are electrically insulated from each other, noise transmission to the LPF 32 is stopped though switching noise is generated in the filter 11 and the circuit 21. Then, the integral value of the signal Y, namely, an analog output corresponding to data X is obtained from the LPF 32. Thus, noise is prevented from being mixed with the analog output. COPYRIGHT: (C)1990,JPO&Japio | ||||||
| 56 | TECHNIQUES FOR PARALLEL DATA DECOMPRESSION | US15393190 | 2016-12-28 | US20180183462A1 | 2018-06-28 | VINODH GOPAL; JAMES D. GUILFORD |
| Techniques and apparatus for parallel decompression are described. In one embodiment, for example, an apparatus to provide parallel decompression may include at least one memory and logic for a decompression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine decompression information of a compressed data unit, annotate the compressed data unit with at least a portion of the decompression information to generate an annotated data unit, parallel-decode the annotated data unit to generate a plurality of intermediate elements, and decode and merge the plurality of intermediate elements to generate a decompressed data unit. Other embodiments are described and claimed. | ||||||
| 57 | Continuous rounding of differing bit lengths | US14677583 | 2015-04-02 | US09450601B1 | 2016-09-20 | Andrew David Daniel |
| A system and method are disclosed for encoding numbers in a way that improves the accuracy and efficiency of one or more computing devices working with the transmitted/stored encoded numbers. When the encoded value is missing one or more bits after transmission or storage, the remaining bits of the encoded value will be optimally rounded up or down for the number of bits actually received. | ||||||
| 58 | APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE | US14490307 | 2014-09-18 | US20160087646A1 | 2016-03-24 | Ravi H. Motwani; Pranav Kalavade |
| Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT. | ||||||
| 59 | DPD/BCD to BID converters | US13644374 | 2012-10-04 | US09143159B2 | 2015-09-22 | Ahmed A. Ayoub; Hossam Aly Hassan Fahmy; Tarek Eldeeb |
| A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors. | ||||||
| 60 | Method and system for dynamic table line encoding | US14148116 | 2014-01-06 | US09100031B1 | 2015-08-04 | Gregg William Baeckler; David W. Mendel |
| Disclosed are systems, apparatus, and methods for encoding data transmitted in a data line. In various embodiments, a device may include a first input port operative to receive a first data value. In some embodiments, the device may further include a first memory device operative to look up a second data value based on the first data value, where the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and where the memory device is operative to be configured according to a plurality of line encoding schemes. In various embodiments, the device may further include a first output port operative to provide an output signal, where the output signal comprises one or more data values including the second data value. | ||||||
QQ群二维码
意见反馈
意见反馈