| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | System and method for conversion of numeric values between different number base formats, for use with software applications | US14504288 | 2014-10-01 | US09729167B2 | 2017-08-08 | Olivier Lagneau; Joseph Darcy |
| Described herein are systems and methods for conversion of numeric values between different number base formats, for use with software applications. In accordance with an embodiment, an integral part of a passed floating-point numeric value in a source number base (e.g., binary) format is isolated and converted to an integer. A fractional part of the numeric value is also isolated and converted to an integer, while limiting the isolation and conversion of the fractional part to a required precision or number of digits, depending on the particular requirements of a software application. The fractional part can be rounded, including determining an exact roundoff as appropriate, and if necessary propagating the rounding to the integral part. Digits from the resulting integers representing the integral and fractional parts can then be collected and used to prepare a representation of the original numeric value in a target number base (e.g., decimal) format. | ||||||
| 102 | Accelerating codeset conversion in a computing environment | US14842868 | 2015-09-02 | US09438269B1 | 2016-09-06 | Jian Li; Zhuo Li; Su Liu; Shunguo Yan |
| A method for accelerating codeset conversion in a computing environment is provided. The method may include, among other things, receiving one or more requests for codeset conversion. The one or more requests may be received, for example, from a client over a communications network. A change in the one or more requests for codeset conversion may be detected. In response to detecting the change, a subset of codeset converters may be selected from among a library of codeset converters to be included in a codeset conversion accelerator. The codeset conversion accelerator may be, among other things, reprogrammed with selected subset of codeset converters. The one or more received requests may be subsequently rerouted to the reprogrammed codeset conversion accelerator. | ||||||
| 103 | Scrambler with built in test capabilities for unary DAC | US14580099 | 2014-12-22 | US09124287B1 | 2015-09-01 | Stanley Ho; William Michael Lye |
| An apparatus comprising a scrambler having a plurality of scrambler inputs and 2N scrambler outputs, and a unary-weighted digital to analog converter (DAC) connected to scrambler to generate an analog output signal based on the 2N scrambler outputs. The scrambler has N unique scrambling stages arranged in order between the scrambler inputs and the scrambler outputs from a first scrambling stage to a last scrambling stage. Each of the N unique scrambling stages has a plurality of stage inputs and outputs, with the stage inputs of the first scrambling stage connected to the scrambler inputs, the stage outputs of each scrambling stage except the last scrambling stage connected to the stage inputs of a next scrambling stage, and the stage outputs of the last scrambling stage connected to the scrambler outputs. Each of the N unique scrambling stages is operable to pass signals at the inputs to the outputs in either an unscrambled or scrambled state under control of a control bit provided by an N-bit entropy signal. When an N+1 bit input signal is applied to the scrambler inputs and the N-bit entropy signal is randomized the analog output signal from the DAC has improved linearity compared to the analog output signal generated from a non-scrambled input, and when a test input signal is applied to the scrambler inputs and the entropy signal is swept through 2N orthogonal values the analog output signal from the DAC indicates whether a fault exists in one of the scrambler and the DAC. | ||||||
| 104 | Codes for Enhancing the Repeated Use of Flash Memory | US14318648 | 2014-06-29 | US20150143197A1 | 2015-05-21 | Shmuel T. KLEIN |
| A basic property of flash memory is that: a 0-bit can be changed into a 1-bit, but not vice-versa, which severely limits the possibilities of reusing storage space with new data. A family of new coding methods is presented that enables double use of the memory, effectively expanding the combined amount of stored data. This can then be used as a compression booster, adding an additional layer to, and improving the compression of some rewriting methods that are not context sensitive. | ||||||
| 105 | Model calculation unit and control unit for calculating a data-based function model having data in various number formats | US14320941 | 2014-07-01 | US20150012574A1 | 2015-01-08 | Wolfgang Fischer; Nico Bannow; Andre Gunturo |
| A model calculation unit for calculating a data-based function model, in particular a Gaussian process model, in a control unit, including: a processor core to carry out a strictly hardware-based calculation of an algorithm for a data-based function model, the data-based function model being calculated using provided calculation data, in particular hyperparameters and node data; and a strictly hardware-based conversion unit to provide the processor core with at least a portion of the calculation data, in particular the provided node data, in a predefined number format. | ||||||
| 106 | Floating point format converter | US13080883 | 2011-04-06 | US08719322B2 | 2014-05-06 | David W. Bishop |
| A computer program product for converting from a first floating point format to a second floating point format, each floating point format having an associated base value and being represented by a significand value and a exponent value, comprising an executable algorithm to perform the steps of: determining the second exponent value by multiplying the first exponent value by a predefined constant and taking the integer portion of the result, the predefined constant being substantially equivalent to the logarithm of the first base value divided by the logarithm of the second base value; determining a bias value substantially equivalent to the second base value raised to the second exponent value divided by the first base value raised to the first exponent value; and determining the second significand value by multiplying the first significand value by the bias value. | ||||||
| 107 | Code set conversion management optimization | US13564553 | 2012-08-01 | US08704687B2 | 2014-04-22 | David N. Clissold; Mark A. Grubbs; Su Liu; Kevin R. Sloan |
| A management module registers a request to convert code from a first code set to a second code set, identifies a code set converter (CSC), determines whether a most recently used CSC is the identified CSC and, in response to determining that the most recently used CSC is not the identified CSC, locates a user-preferred CSC pool comprising a subset of locally stored CSCs each corresponding to a preference index. The management module, in response to determining that the identified CSC is located within the user-preferred CSC pool, searches the user-preferred CSC pool for the identified CSC, loads the identified CSC, initiates the identified CSC that converts the code from the first code set to the second code set, modifies usage data for the identified CSC, and orders the user-preferred CSC pool based on a preference index for each CSC stored in the CSC pool. | ||||||
| 108 | DPD/BCD TO BID CONVERTERS | US13644374 | 2012-10-04 | US20140101215A1 | 2014-04-10 | Ahmed A. Ayoub; Hossam Aly Hassan Fahmy; Tarek Eldeeb |
| A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors. | ||||||
| 109 | Configuring floating point operations in a programmable device | US12625800 | 2009-11-25 | US08650231B1 | 2014-02-11 | Martin Langhammer |
| A programmable device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step. To conserve resources, rather than configuring the every intermediate operation to have the same mantissa size, in the internal format the mantissa size may start out smaller and grow after each operation. | ||||||
| 110 | DATA TRANSLATION SYSTEM AND METHOD | US13944819 | 2013-07-17 | US20140028479A1 | 2014-01-30 | Frank N.G. Cheung |
| A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function, (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output. | ||||||
| 111 | APPARATUS AND METHOD FOR CODING DATA BASED ON PHASOR DISPARITY | US14006702 | 2011-10-01 | US20140009315A1 | 2014-01-09 | Dawson W. Kesling; Maynard C. Falconer; Kevin P. Slattery; Harry G. Skinner |
| A method for managing information includes receiving bits of data, determining phasors for bits at only one frequency of a transmission spectrum, combining the phasors of bits that form a phasor having a spectral energy that lies within a predetermined range, and forming a codeword from the bits of the combined phasors. | ||||||
| 112 | Data translation system and method | US11454689 | 2006-06-16 | US08495335B2 | 2013-07-23 | Frank N. G. Cheung |
| A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output. | ||||||
| 113 | Method and apparatus for digital to analog conversion of data stream with random and low-frequency periodic jitter | US12350884 | 2009-01-08 | US08350734B1 | 2013-01-08 | Andrew Martin Mallinson |
| This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims. | ||||||
| 114 | FLOATING POINT FORMAT CONVERTER | US13080883 | 2011-04-06 | US20120259904A1 | 2012-10-11 | David W. Bishop |
| A computer program product for converting from a first floating point format to a second floating point format, each floating point format having an associated base value and being represented by a significand value and a exponent value, comprising an executable algorithm to perform the steps of: determining the second exponent value by multiplying the first exponent value by a predefined constant and taking the integer portion of the result, the predefined constant being substantially equivalent to the logarithm of the first base value divided by the logarithm of the second base value; determining a bias value substantially equivalent to the second base value raised to the second exponent value divided by the first base value raised to the first exponent value; and determining the second significand value by multiplying the first significand value by the bias value. | ||||||
| 115 | Systems and methods for optimizing bit utilization in data encoding | US12780354 | 2010-05-14 | US07978924B2 | 2011-07-12 | Stephen C. Palmer; Richard Wyatt |
| In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme. | ||||||
| 116 | Data coding buffer for electrical computers and digital data processing systems | US12463584 | 2009-05-11 | US07843367B2 | 2010-11-30 | Donald M. Monro |
| A method includes receiving, at a decoding device, first contents of a buffer, where the first contents of the buffer include at least a first data symbol. The first data symbol is coded into the first contents of the buffer based at least in part on a first radix of the first data symbol. The first data symbol is decoded from the first contents of the buffer. Based at least in part on the first radix of the first data symbol, it is determined whether the first contents of the buffer include a second data symbol. The second data symbol is decoded from the first contents of the buffer if the first contents include the second data symbol. | ||||||
| 117 | SYSTEMS AND METHODS FOR OPTIMIZING BIT UTILIZATION IN DATA ENCODING | US12780354 | 2010-05-14 | US20100219994A1 | 2010-09-02 | Stephen C. Palmer; Richard Wyatt |
| In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme. | ||||||
| 118 | Modulation coding and decoding | US12262297 | 2008-10-31 | US07786906B2 | 2010-08-31 | Thomas Mittelholzer |
| Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided. | ||||||
| 119 | Systems and methods for optimizing bit utilization in data encoding | US11474990 | 2006-06-27 | US07738717B1 | 2010-06-15 | Stephen C. Palmer; Richard Wyatt |
| In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme. | ||||||
| 120 | Data coding/decoding for electrical computers and digital data processing systems | US11776786 | 2007-07-12 | US07602316B2 | 2009-10-13 | Donald M. Monro |
| Embodiments of methods, systems and/or devices for data coding are disclosed. Briefly, in accordance with one embodiment, data is coded and transmitted via an input/output portion of a computing platform to one or more other portions of the computing platform. An interconnect is employed to facilitate transmitting the coded data. | ||||||
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