| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | Methods and systems for low weight coding | US13778045 | 2013-02-26 | US08952834B1 | 2015-02-10 | Harm Cronie |
| Methods and circuits are described for creating low-weight codes, encoding of data as low-weight codes for communication or storage, and efficient decoding of low-weight codes to recover the original data. Low-weight code words are larger than the data values they encode, and contain a significant preponderance of a single value, such as zero bits. The resulting encoded data may be transmitted with significantly lower power and/or interference. | ||||||
| 62 | Data translation system and method | US13944819 | 2013-07-17 | US08868881B2 | 2014-10-21 | Frank N. G. Cheung |
| A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function, (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output. | ||||||
| 63 | Methods and apparatuses for converting floating point representations | US12947699 | 2010-11-16 | US08745111B2 | 2014-06-03 | Ian R. Ollmann |
| A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number. | ||||||
| 64 | CODE SET CONVERSION MANAGEMENT OPTIMIZATION | US13564553 | 2012-08-01 | US20140035764A1 | 2014-02-06 | David N. Clissold; Mark A. Grubbs; Su Liu; Kevin R. Sloan |
| A management module registers a request to convert code from a first code set to a second code set, identifies a code set converter (CSC), determines whether a most recently used CSC is the identified CSC and, in response to determining that the most recently used CSC is not the identified CSC, locates a user-preferred CSC pool comprising a subset of locally stored CSCs each corresponding to a preference index. The management module, in response to determining that the identified CSC is located within the user-preferred CSC pool, searches the user-preferred CSC pool for the identified CSC, loads the identified CSC, initiates the identified CSC that converts the code from the first code set to the second code set, modifies usage data for the identified CSC, and orders the user-preferred CSC pool based on a preference index for each CSC stored in the CSC pool. | ||||||
| 65 | Method and system for dynamic table line encoding | US13563533 | 2012-07-31 | US08638245B1 | 2014-01-28 | Gregg William Baeckler; David W. Mendel |
| Disclosed are systems, apparatus, and methods for encoding data transmitted in a data line. In various embodiments, a device may include a first input port operative to receive a first data value. In some embodiments, the device may further include a first memory device operative to look up a second data value based on the first data value, where the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and where the memory device is operative to be configured according to a plurality of line encoding schemes. In various embodiments, the device may further include a first output port operative to provide an output signal, where the output signal comprises one or more data values including the second data value. | ||||||
| 66 | Systems and methods for optimizing bit utilization in data encoding | US13155049 | 2011-06-07 | US08509554B2 | 2013-08-13 | Stephen C. Palmer; Richard Wyatt |
| In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme. | ||||||
| 67 | METHODS AND APPARATUSES FOR CONVERTING FLOATING POINT REPRESENTATIONS | US12947699 | 2010-11-16 | US20120124115A1 | 2012-05-17 | Ian R. Ollmann |
| A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number. | ||||||
| 68 | SYSTEMS AND METHODS FOR OPTIMIZING BIT UTILIZATION IN DATA ENCODING | US13155049 | 2011-06-07 | US20110234432A1 | 2011-09-29 | Stephen C. Palmer; Richard Wyatt |
| In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme. | ||||||
| 69 | Configuring floating point operations in a programmable logic device | US11625655 | 2007-01-22 | US07865541B1 | 2011-01-04 | Martin Langhammer |
| A programmable logic device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step. | ||||||
| 70 | Constant weight coding of signals based on conjugate dissections | US11881653 | 2007-07-27 | US07791511B1 | 2010-09-07 | Neil James Alexander Sloane; Vinay Anant Vaishampayan |
| A method for encoding and decoding codes of constant weight that is based on conjugate dissections, which progressively modifies element values of an input vector to satisfy the constraint that each encoded symbol is to comprise integer component elements even when the encoded symbol is generated through processing that involved permuting. | ||||||
| 71 | Voltage level digital system | US12291138 | 2008-11-05 | US07786904B1 | 2010-08-31 | Mingchih Hsieh |
| A digital system programmed to accept words wherein each of said words is a collection of “bit” voltage values with each bit value represented by its position in the word and the value of a base raised to a power, said base multiplied by an integer, m. | ||||||
| 72 | DATA CODING BUFFER FOR ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS | US12463584 | 2009-05-11 | US20090219180A1 | 2009-09-03 | Donald Martin Monro |
| A method includes receiving, at a decoding device, first contents of a buffer, where the first contents of the buffer include at least a first data symbol. The first data symbol is coded into the first contents of the buffer based at least in part on a first radix of the first data symbol. The first data symbol is decoded from the first contents of the buffer. Based at least in part on the first radix of the first data symbol, it is determined whether the first contents of the buffer include a second data symbol. The second data symbol is decoded from the first contents of the buffer if the first contents include the second data symbol. | ||||||
| 73 | DATA CODING/DECODING FOR ELECTRICAL COMPUTERS AND DIGITAL DATA PROCESSING SYSTEMS | US11776786 | 2007-07-12 | US20090019069A1 | 2009-01-15 | Donald Martin Monro |
| Embodiments of methods, systems and/or devices for data coding are disclosed. Briefly, in accordance with one embodiment, data is coded and transmitted via an input/output portion of a computing platform to one or more other portions of the computing platform. An interconnect is employed to facilitate transmitting the coded data. | ||||||
| 74 | Device with dB-to-linear gain conversion | US10603030 | 2003-06-24 | US07321912B2 | 2008-01-22 | Rustin W. Allred |
| An electronic dB-to-linear gain conversion system (10). The system comprises an input (12) for receiving a gain index signal (GI) representing a desired dB value. The desired dB value is selected from a set having an integer number S of dB values. The system also comprises a storage circuit (16) for storing an integer number V of linear gain values and circuitry for producing a linear gain signal (LG) in response to the gain index signal and to one of the V linear gain values. In the preferred embodiment, V is less than S. | ||||||
| 75 | Device with dB-to-linear gain conversion | US10603030 | 2003-06-24 | US20040267842A1 | 2004-12-30 | Rustin W. Allred |
| An electronic dB-to-linear gain conversion system (10). The system comprises an input (12) for receiving a gain index signal (GI) representing a desired dB value. The desired dB value is selected from a set having an integer number S of dB values. The system also comprises a storage circuit (16) for storing an integer number V of linear gain values and circuitry for producing a linear gain signal (LG) in response to the gain index signal and to one of the V linear gain values. In the preferred embodiment, V is less than S. | ||||||
| 76 | Examination of residues of data-conversions | US09436851 | 1999-11-09 | US06694344B1 | 2004-02-17 | Guenter Gerwig; Juergen Haess; Michael Kroener; Erwin Pfeffer |
| A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure. | ||||||
| 77 | Multiplexing an additional bit stream with a primary bit stream | US10245854 | 2002-09-17 | US20030161353A1 | 2003-08-28 | Jerchen Kuo; Gerry Pesavento |
| Multiplexing an additional bit stream with a primary bit stream, where the primary bit stream is encoded into an xB/yB encoded bit stream, involves selecting yB code-words to convey the additional bit stream. Each xB word is represented by one yB code-word from a corresponding group of yB code-words, with each group of yB code-words including at least one yB code-word belonging to a category of code-words that tends to exhibit positive DC balance and at least one yB code-word belonging to a category that tends to exhibit negative DC balance. Bits of the additional bit stream are multiplexed with the primary bit stream by selecting code-words from one of the two categories to convey 1's and from the other category to convey 0's. Code-words that are not selected to convey bits of the additional bit stream are selected to balance the running disparity of the encoded bit stream. | ||||||
| 78 | Encoder and decoder | US09233000 | 1999-01-19 | US06229461B1 | 2001-05-08 | Fumiaki Nagao |
| To encode data Y after separating the data Y into a scale factor SF, a word length, and a data value X. For this purpose, X=Y·{2(WL−1)−1}/SF is calculated. Here, a value of {2(WL−1)−1}/SFV with respect to a number of SFV and a number of SL, which are obtained by separating into SF=SF·2SFF, is stored in a ROM in advance. Then, input data Y is separated into a mantissa part Yr and an index part Ye and Ye is added to SFF. Then, the shifter 16 shifts Yr according to an additional result to obtain Ye·2Ye·2SFF. On the other hand, based on SF and WL, which are determined with respect to Y, a value of corresponding {2(WL−1)−1}/SFV is read from the ROM. Then, the shifted result is multiplied by the output from the ROM to obtain a data value X. Also, Y=SF·X/{2(WL−1)−1} is calculated and decoded. Inputted SF is divided into SFV and SFF. Based on the obtained SFV and inputted WL, a value of corresponding SFV/{2(WL−1)−} is read from the ROM. SFF is given as an index value for the inputted X. The result with the index value given and the output from the ROM are multiplied in a multiplier to calculate Y to decode. | ||||||
| 79 | Binary encoding method with substantially uniform rate of changing of the binary elements and corresponding method of incrementation and decrementation | US784545 | 1991-10-29 | US5300930A | 1994-04-05 | M. Jacques Burger; M. Marc Girault |
| A binary encoding method notably but not exclusively for the encoding of data elements designed to be represented sequentially, according to a preestablished order, for example in counters, inducing a uniform or substantially uniform mean changing rate for each of the binary elements, the data elements being encoded on two distinct fields of binary elements, a reference field and a permutation field, and the sequence of binary elements assigned to the permutation field undergoing a permutation as a function of the value contained in the reference field. | ||||||
| 80 | Digital-to-analog conversion circuit | US514859 | 1990-04-26 | US5019819A | 1991-05-28 | Shigenobu Kimura |
| A digital-to-analog conversion circuit capable of preventing a noise produced in a digital system from mixing in an analog output has an input circuit receiving a pulse-code modulated digital signal, a conversion circuit such as a noise shaping circuit for converting the pulse-code modulated digital signal to a pulse wave signal containing analog amplitude information in a time axis direction, a buffer circuit including an electrically insulated coupling circuit such as an optical coupling circuit for transmitting output of the conversion circuit, and an analog output circuit including an analog low-pass filter for delivering out output of the buffer circuit therethrough. A noise generated in a digital system is intercepted by the buffer circuit and is not transmitted further so that mixing of the noise in the analog output circuit is prevented. | ||||||
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