To suppress noise generation in a wide band and to suppress a clock speed from being increased in a sigma-delta modulation apparatus and a sigma-delta modulation power amplifier. A sigma-delta modulator creates a sigma-delta modulated signal for a digital output from a digital modulator, according to a clock given in advance. A threshold comparator indexes a portion in which the level of a digital output from the digital modulator is higher than a predetermined threshold and sends the resulting output. A replacing unit replaces the indexed portion with an output from a corresponding thinning unit. A filter unit performs band elimination filter processing on an output from the replacing unit and a digital-to-analog converter (D/A) performs digital-to-analog conversion on an output from the filter unit.

The present disclosure describes an improved multi-stage noise shaping (MASH) analogto-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (Δ∑) modulator is provided at the front-end of the MASH ADC, and another full Δ∑ modulator is provided at the back-end of the MASH ADC. The front-end Δ∑ modulator digitizes an analog input signal, and the back-end Δ∑ modulator digitizes an error between the output of the front-end Δ∑ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and a resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to "residual quantization error," which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

An error averaging comparator based switch capacitor (CBSC) circuit cyclically operates through a sampling phase, a first transfer phase, and a second transfer phase. During the sampling phase, an input voltage is sampled. During the first transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to a first load. During the second transfer phase, the sampled input voltage is amplified by the same fixed ratio and transferred to a second load. The circuit configuration during the second transfer phase is substantially the same as that during the first transfer phase, except that the at least one of its circuit elements is connected in a reverse polarity. Due to the reverse polarity, the respective errors due to circuit non-idealities during the two transfer phases are exactly opposite. By combining the outputs taken at the first load and at the second load, the errors are averaged out.