| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 201 | Methods and devices for error correction of a signal using delta sigma modulation | US14907596 | 2013-11-28 | US09520886B2 | 2016-12-13 | Donald Jeffrey Dionne; Brian Leonard William Howse; Jennifer Marie McCann |
| A method for correcting long-term phase drift of a crystal oscillator in a numerically-controlled oscillator is described. The method includes determining the phase error in an oscillator signal in comparison with an external time base; delta-sigma modulating the phase error to generate a delta-sigma error bitstream; conditionally adding or subtracting an error correction step size from a phase increment value in each clock cycle based on the delta-sigma error bitstream, to create a modulated phase increment value; and adding the modulated phase increment value to a phase accumulator to generate an error-corrected output digital signal. The delta-sigma-based error correction method avoids the use of multipliers. The same delta-sigma error signal can be used in multiple numerically-controlled oscillators configured to different output frequency if driven by the same reference oscillator. | ||||||
| 202 | Resonance circuit used for measurement device and measurement device | US15015262 | 2016-02-04 | US09518854B2 | 2016-12-13 | Yuki Ikadai; Masami Wada |
| A resonance circuit is configured to receive a pulse density signal obtained by ΔΣ-modulating an analog displacement signal by a ΔΣ modulator and a multi-bit signal obtained from the pulse density signal and to generate an excitation signal based on the pulse density signal and the multi-bit signal. The resonance circuit includes an amplification factor controller configured to set an amplification factor depending on a vibration signal obtained from the multi-bit signal, a multiplier configured to amplify a level of the pulse density signal by the amplification factor, and a circuit group configured to generate the excitation signal based on a pulse density signal obtained by further ΔΣ-modulating an output of the multiplier. The amplification factor controller is configured to set the amplification factor using a proportional control and an integral control based a difference between an amplitude signal obtained from the vibration signal and a target amplitude value. | ||||||
| 203 | METHOD AND APPARATUS FOR ENCODING ANALOG SIGNAL INTO TIME INTERVALS | US14972468 | 2015-12-17 | US20160344402A1 | 2016-11-24 | Dariusz KOSCIELNIK; Marek MISKOWICZ |
| Method for encoding analog signal into time intervals wherein a generation of time intervals using a time encoding machine. A signal of a constant value is held during a generated time interval on a time encoding machine input by the use of a sample-and-hold circuit, while the constant value of the signal held during the generated time interval represents an instantaneous value of the analog signal at the end of a generation of a previous time interval. Apparatus for encoding analog signal into time intervals comprising a time encoding machine, and a sample-and-hold circuit. The signal is provided to an input of the sample-and-hold circuit, whose output is connected to an output of the time encoding machine. The output of the time encoding machine is connected to an output of the apparatus, and to a control input of the sample-and-hold circuit. | ||||||
| 204 | Motor drive voltage control device and method for controlling motor drive voltage | US14648289 | 2013-12-12 | US09503013B2 | 2016-11-22 | Junichi Urata; Masayuki Inaba |
| To suppress a decline in the control accuracy of an applied voltage associated with an increase in quantum noise, and to increase the control accuracy of a motor speed. When generating a driving voltage signal supplied to a motor from a driving command signal, a motor-driving voltage control device reduces the gradation level and performs noise-shaping modulation before performing PWM modulation. Reducing the gradation level allows the degree of gradation of the driving voltage signal to be within the resolution range of the PWM modulation, and thus PWM modulation can be performed even when the driving voltage signal has a high frequency. Noise-shaping modulation reduces the level of quantum noise near the low frequency range by causing the quantum noise due to digitization, included in the driving voltage signal, to be biased toward the high frequency range side. Of modulation signals with the reduced-gradation level, the components near the high frequency band are cut, while the components near the low frequency range are used to suppress quantum noise and control the driving voltage applied to the motor with a high accuracy. | ||||||
| 205 | Techniques for Fractional-N Phase Locked Loops | US14383865 | 2014-05-16 | US20160248431A1 | 2016-08-25 | Kexin LUO; Kai ZHOU; Shengguo CAO; Lingfen YUE; Fangquing CHU; Yu SHEN; Zhi WU |
| Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a factional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL. | ||||||
| 206 | SIGNAL MODULATION CIRCUIT | US15137129 | 2016-04-25 | US20160241256A1 | 2016-08-18 | Yoshinori NAKANISHI; Tsuyoshi KAWAGUCHI; Mamoru SEKIYA |
| Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed. | ||||||
| 207 | System, circuit and method for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal for battery voltage managment | US14592736 | 2015-01-08 | US09419644B2 | 2016-08-16 | Anthony John Allen |
| A system, circuit and method for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal are disclosed. For example, a circuit for converting a differential voltage signal including a high common mode voltage component to a ground referenced signal is disclosed. The circuit includes a comparator configured to receive a differential voltage signal including a high common mode voltage component, and output a digital signal associated with the differential voltage signal. The circuit also includes a level shifter configured to receive the digital signal and shift the level of the digital signal to a low level, and an integrator configured to receive the digital low level signal and output a ramping voltage associated with the low level signal. Furthermore, the circuit includes an analog-to-digital converter configured to receive the ramping voltage and output a digital bit-stream associated with the ramping voltage. | ||||||
| 208 | RESONANCE CIRCUIT USED FOR MEASUREMENT DEVICE AND MEASUREMENT DEVICE | US15015262 | 2016-02-04 | US20160231156A1 | 2016-08-11 | Yuki IKADAI; Masami WADA |
| A resonance circuit is configured to receive a pulse density signal obtained by ΔΣ-modulating an analog displacement signal by a ΔΣ modulator and a multi-bit signal obtained from the pulse density signal and to generate an excitation signal based on the pulse density signal and the multi-bit signal. The resonance circuit includes an amplification factor controller configured to set an amplification factor depending on a vibration signal obtained from the multi-bit signal, a multiplier configured to amplify a level of the pulse density signal by the amplification factor, and a circuit group configured to generate the excitation signal based on a pulse density signal obtained by further ΔΣ-modulating an output of the multiplier. The amplification factor controller is configured to set the amplification factor using a proportional control and an integral control based a difference between an amplitude signal obtained from the vibration signal and a target amplitude value. | ||||||
| 209 | Distributed Combiner for Parallel Discrete-to-Linear Converters | US14996497 | 2016-01-15 | US20160226509A1 | 2016-08-04 | Christopher Pagnanelli |
| Provided are, among other things, systems, apparatuses methods and techniques for providing a complete output signal from a set of partial signals, which in turn have been generated by parallel processing paths in the time-interleaved and/or frequency-interleaved conversion of discrete signals to linear signals (i.e., discrete-to-linear conversion). One such apparatus includes a distributed network comprising a plurality of ladder networks through which input signals propagate before being combined to form an output signal. | ||||||
| 210 | Mostly-digital open-loop ring oscillator delta-sigma ADC and methods for conversion | US14302626 | 2014-06-12 | US09397691B2 | 2016-07-19 | Ian Galton; Gerry Taylor |
| A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects digital values based upon the nonlinear distortion coefficients. | ||||||
| 211 | Systems and methods of low power decimation filter for sigma delta ADC | US14754022 | 2015-06-29 | US09391634B1 | 2016-07-12 | Sundarrajan Rangachari |
| Example embodiments of the systems and methods of low power decimation filter exploit the single bit data input to the filter and the symmetry of the filter response. The input data may be treated as 0 and 1 instead of −1 and +1. The symmetry of the sinc filter may be exploited since the data across different polyphases are combined. The addition of the symmetric data and coefficient multiplication may be replaced with simple muxing based on two bits and the use of unsigned logic for all adders following coefficient multiplication as both data and coefficient are non-negative. | ||||||
| 212 | Digital-to-analog converter for reducing pop noise and harmonic tone and related converting method | US12490345 | 2009-06-24 | US09391633B2 | 2016-07-12 | Wei-Chun Lin; Yi-Chang Tu |
| A digital-to-analog converting (DAC) circuit is utilized for converting a 1-bit stream into an analog output signal. The DAC includes an N-bit encoder, a multiplexer, a low-pass filter, and a digital-to-analog conversion circuit. The N-bit encoder is utilized for receiving the 1-bit stream and encoding the 1-bit stream to generate an N-bit stream, where N is larger than 1; the multiplexer is utilized for selectively outputting the N-bit stream or a zero signal as an output signal according to a selection signal; the low-pass filter is utilized to generate a filtered output signal according to the output signal; and the digital to analog conversion circuit is utilized to generate the analog output signal according to the filtered output signal. | ||||||
| 213 | Synchronous modulation resonator with sigma delta modulator | US14794722 | 2015-07-08 | US09379733B1 | 2016-06-28 | Te-Hsi Terrence Lee |
| A Synchronous Modulation Resonator (SMR) device, the device includes a resonator having coupled to a Vd source and a Vr source, wherein the Vd is DC biased, wherein the Vr is AC, wherein the resonator provides a resonator output in response to Vd and Vr, a Sigma Delta Modulator (SDM) coupled to the resonator and to the Vr source, wherein the SDM provides a signal output in response to the resonator output and to the Vr, and a digital output block coupled to the SDM, wherein the digital output block is configured to provide a digital signal representation of the resonator output, in response to the signal output. | ||||||
| 214 | Delta-sigma modulator with reduced integrator requirements | US14845899 | 2015-09-04 | US09379732B2 | 2016-06-28 | John L. Melanson; Stephen T. Hodapp |
| Requirements placed on the first integrator of a filter in a continuous-time delta-feedback modulator may be reduced by using circuitry to reduce the speed of a signal provided to the first integrator of the modulator. The reduction in speed applied to the signal received at the first integrator may then be compensated with circuitry elsewhere in the modulator, such that the net effect of the slow down and speed up of signals does not affect the output of the modulator. The sigma-delta modulator may be implemented in converters, such as an analog-to-digital converter (ADC). | ||||||
| 215 | Electrical signal conversion with reduced-distance element rotation | US14571274 | 2014-12-15 | US09350371B2 | 2016-05-24 | Trevor Clifford Caldwell; Richard E. Schreier; David Alldred; Wenhua W. Yang |
| In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction. | ||||||
| 216 | MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS), APPARATUS, AND OPERATING METHODS THEREOF | US14989056 | 2016-01-06 | US20160118993A1 | 2016-04-28 | Yung-Chow PENG; Wen-Hung HUANG; Yu-Wei LIN |
| A method that comprises converting a first electrical signal to a second electrical signal using a converter coupled between a micro-mechanical structure and an analog-to-digital converter (ADC). The method also comprises actuating a switch to selectively interpolate at least one datum between two neighboring converted second electrical signals based on a selected clock signal, wherein the selected clock signal is one of a plurality of clock signals, each clock signals of the plurality of clock signals has a corresponding frequency, and the selected clock signal corresponds to an operating mode of the micro-mechanical structure. | ||||||
| 217 | Excess loop delay compensation (ELC) for an analog to digital converter (ADC) | US14475852 | 2014-09-03 | US09325341B2 | 2016-04-26 | Elias Hani Dagher; Kentaro Yamamoto; Dinesh Jagannath Alladi |
| In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal. | ||||||
| 218 | Frequency synthesizer and related method for improving power efficiency | US14557462 | 2014-12-02 | US09300305B1 | 2016-03-29 | Chun-Ming Kuo; Chii-Horng Chen; Shih-Chi Shen |
| A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock. | ||||||
| 219 | DIRECT DIGITAL SYNTHESIS OF SIGNALS USING MAXIMUM LIKELIHOOD BIT-STREAM ENCODING | US14944184 | 2015-11-17 | US20160072647A1 | 2016-03-10 | Kameran Azadet; Steven C. Pinault |
| Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal. | ||||||
| 220 | EMBEDDED OVERLOAD PROTECTION IN DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS | US14477236 | 2014-09-04 | US20160072275A1 | 2016-03-10 | TREVOR CLIFFORD CALDWELL; COREY PETERSEN; DAVID NELSON ALLDRED; HAJIME SHIBATA |
| Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected. | ||||||
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