| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 221 | A/D converter | US14819767 | 2015-08-06 | US09281837B2 | 2016-03-08 | Tomohiro Nezuka |
| An A/D converter includes a delta-sigma processing circuit for A/D conversion by delta-sigma modulation, and a cyclic processing circuit for A/D conversion by cyclic processing of amplification of a residue generated in the A/D conversion. The A/D converter further includes a quantization part for outputting a quantized value of quantized output of the delta-sigma processing circuit and a quantized output of the cyclic processing circuit, and a control circuit for generating an A/D conversion result and switching over a reference voltage based on the quantized value. The delta-sigma processing circuit and the cyclic processing circuit include a sampling capacitor, an integration capacitor and a capacitive D/A converter, which includes a DAC capacitor and add and subtract a charge corresponding to a reference voltage to and from a residue of quantization. The sampling capacitor, the DAC capacitor and the integration capacitor are provided as electrically separate capacitors. | ||||||
| 222 | Method and device for producing a digital signal | US14763450 | 2014-01-24 | US09270294B2 | 2016-02-23 | Dirk Duesterberg; Heiko Stichweh |
| A method is provided for generating a digital signal from an analog signal generated using a frequency converter on the basis of pulse width modulation with a variable period duration, values of the digital signal corresponding to an average value of the analog signal over an associated period duration of the pulse width modulation. The method includes the acts of: generating a bit stream on the basis of the analog signal using a sigma-delta modulator, the bit stream being generated with a constant modulator clock; generating temporally successive digital samples during an associated period duration by filtering the bit stream using a number of digital filters, intervals of time between the temporally successive digital samples being multiples of the modulator clock, the digital filters being started with a time delay with respect to one another in the intervals of time of the multiples of the modulator clock, and a respective digital filter outputting an associated digital sample, and forming an average value of the digital samples generated during the associated period duration, the average value forming the value of the digital signal (DS) for the associated period duration. | ||||||
| 223 | SIGNAL PROCESSING | US14341216 | 2014-07-25 | US20160028380A1 | 2016-01-28 | Kevin Townsend |
| A method of processing an amplitude-modulated analogue signal at a carrier frequency Fc comprises: digitising the analogue signal to produce an input bit stream that represents the amplitude of the analogue signal; generating an in-phase reference bit stream that is synchronous to the carrier frequency Fc and represents an in-phase digital reference signal substantially in the form of a sine and/or cosine wave; and multiplying the input bit stream with the in-phase reference bit stream to produce an output bit stream representing the amplitude modulation of the analogue signal. | ||||||
| 224 | Idle tone dispersion device and frequency measurement device | US14712087 | 2015-05-14 | US09231613B2 | 2016-01-05 | Masayoshi Todorokihara |
| An idle tone dispersion device includes n FDSM (1) to FDSM (n), a phase adjustment unit which relatively adjusts a phase between a measured signal and a reference signal such that a phase of an idle tone is completely different, and generates and supplies n sets of output measured signals and output reference signals to each of the n FDSM (1) to FDSM (n), and an adder which adds output data of the n FDSM (1) to FDSM (n) and outputs a frequency delta-sigma modulation signal. | ||||||
| 225 | Sigma-delta analog-to-digital converter | US14659639 | 2015-03-17 | US09219495B2 | 2015-12-22 | Xiaomin Si |
| The application disclose a sigma-delta analog-to-digital converter. The converter comprises: a summing stage, configured to receive an input signal and subtract a first feedback signal and a second feedback signal from the input signal to generate a difference signal; a loop filter coupled to an output node of the summing stage, and configured to filter the difference signal; a quantizer coupled to an output node of the loop filter, and configured to quantize the filtered difference signal to generate a quantized signal, and to generate an overload signal according to the filtered difference signal, wherein the overload signal indicates whether the filtered difference signal is overloaded and/or an overload amount of the filtered difference signal; a first digital-to-analog converter coupled to the quantizer to receive the quantized signal, and configured to generate the first feedback signal according to the quantized signal; and a second D/A converter coupled to the quantizer to receive the overload signal, and configured to generate the second feedback signal according to the overload signal. | ||||||
| 226 | FEED FORWARD DOUBLE-SAMPLING MODULATOR | US14305184 | 2014-06-16 | US20150365102A1 | 2015-12-17 | Jose Luis CEBALLOS; Christian REINDL; Snezana STOJANOVIC |
| Representative implementations of devices and techniques provide analog to digital conversion of an analog input. A multistage modulator using a feed-forward technique can alternately convert integrated samples of the analog input to digital representations. For example, the modulator is arranged to alternately output the digital representations to form a digital representation of the analog input. | ||||||
| 227 | Maximum likelihood bit-stream generation and detection using M-algorithm and infinite impulse response filtering | US14090555 | 2013-11-26 | US09201628B2 | 2015-12-01 | Kameran Azadet; Steven C. Pinault |
| Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal. | ||||||
| 228 | MEASUREMENT METHOD, MEASUREMENT APPARATUS AND MEASUREMENT PROGRAM | US14392047 | 2013-10-13 | US20150318866A1 | 2015-11-05 | Mitsutoshi Sugawara |
| [Problem] To shorten the measurement time, while maintaining the measurement precision, for a data converter of delta-sigma system.[Solution] A measurement method of the present embodiment is a measurement method for a delta-sigma type of data converter that performs a data conversion between an analog signal and a digital signal. The measurement method comprises:successively measuring and taking in output digital codes outputted via data conversions performed, by a data converter, on the basis of ramp-waveform inputs generated on the basis of input voltage values at predetermined intervals; selecting and pairing, as pair combinations, those ones of the output digital codes which are different from each other and further adjacent to each other in order of magnitude of value; performing, for each combination, a predetermined statistical processing by use of the output digital codes belonging to the combination or by use of the input voltage values corresponding to these output digital codes; and calculating a nonlinear error from the result of the statistical processing. | ||||||
| 229 | Communication unit, digital band-pass sigma-delta modulator and method therefor | US14574568 | 2014-12-18 | US09166617B1 | 2015-10-20 | Hugues Beaulaton; Jean-Christophe Nanan |
| A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch. | ||||||
| 230 | Sigma-Delta Analog-to-Digital Converter | US14659639 | 2015-03-17 | US20150280734A1 | 2015-10-01 | Xiaomin Si |
| The application disclose a sigma-delta analog-to-digital converter. The converter comprises: a summing stage, configured to receive an input signal and subtract a first feedback signal and a second feedback signal from the input signal to generate a difference signal; a loop filter coupled to an output node of the summing stage, and configured to filter the difference signal; a quantizer coupled to an output node of the loop filter, and configured to quantize the filtered difference signal to generate a quantized signal, and to generate an overload signal according to the filtered difference signal, wherein the overload signal indicates whether the filtered difference signal is overloaded and/or an overload amount of the filtered difference signal; a first digital-to-analog converter coupled to the quantizer to receive the quantized signal, and configured to generate the first feedback signal according to the quantized signal; and a second D/A converter coupled to the quantizer to receive the overload signal, and configured to generate the second feedback signal according to the overload signal. | ||||||
| 231 | COMMUNICATION UNIT, DIGITAL BAND-PASS SIGMA-DELTA MODULATOR AND METHOD THEREFOR | US14574568 | 2014-12-18 | US20150280732A1 | 2015-10-01 | HUGUES BEAULATON; JEAN-CHRISTOPHE NANAN |
| A communication unit comprises a power DAC. The DAC comprises: a switched mode power amplifier (SMPA); and a digital band-pass sigma-delta modulator operably coupled to the SMPA. The sigma-delta modulator comprises an input to receive an input baseband signal; a delay; an adder module arranged to add a feedback signal with an output from the delay; and at least two feedback branches. The sigma-delta modulator is arranged to digitally oversample the input baseband signal such that a ratio of a sampling frequency employed by the sigma-delta modulator to a radio frequency (RF) output from the DAC is fixed and the sampling frequency tuned or wherein the sampling frequency is fixed and the ratio is adjusted, such that a first feedback branch in the sigma-delta modulator is formed using at least one from a group of: a zero gain, an additive inverse of a second feedback branch. | ||||||
| 232 | Delta-sigma A/D converter | US13523592 | 2012-06-14 | US09118341B2 | 2015-08-25 | Takashi Matsumoto; Toshio Kumamoto; Takashi Okuda |
| A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer. | ||||||
| 233 | Flash converter capacitance reduction method | US14272708 | 2014-05-08 | US09100041B1 | 2015-08-04 | Justin Richardson; Mairead Kelly; Andrew Myles |
| A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise. | ||||||
| 234 | DELTA-SIGMA MODULATOR | US14308752 | 2014-06-19 | US20150200678A1 | 2015-07-16 | Young Kyun CHO; JAE HO JUNG; Kwangchun LEE |
| Provided is a delta-sigma modulator including a summer summing an input signal and an analog signal, a first integrator integrating an output signal from the summer and outputting a first integration signal, a second integrator integrating the first integration signal and outputting a second integration signal, a comparator comparing the second integration signal and a reference signal and outputting a digital signal according to the comparison result, and a digital-to-analog converter converting the digital signal into an analog signal in response to a clock signal and outputting the converted analog signal, wherein the second integrator operates based on an Nth order (where N is natural number of 1 or greater) transfer function. | ||||||
| 235 | SIGMA-DELTA MODULATION APPARATUS AND SIGMA-DELTA MODULATION POWER AMPLIFIER | US14543954 | 2014-11-18 | US20150188740A1 | 2015-07-02 | Shigeo KUSUNOKI |
| To suppress noise generation in a wide band and to suppress a clock speed from being increased in a sigma-delta modulation apparatus and a sigma-delta modulation power amplifier. A sigma-delta modulator creates a sigma-delta modulated signal for a digital output from a digital modulator, according to a clock given in advance. A threshold comparator indexes a portion in which the level of a digital output from the digital modulator is higher than a predetermined threshold and sends the resulting output. A replacing unit replaces the indexed portion with an output from a corresponding thinning unit. A filter unit performs band elimination filter processing on an output from the replacing unit and a digital-to-analog converter (D/A) performs digital-to-analog conversion on an output from the filter unit. | ||||||
| 236 | Quantization noise coupling delta sigma ADC with a delay in the main DAC feedback | US14301948 | 2014-06-11 | US09054733B2 | 2015-06-09 | Vincent Quiquempoix; Fabien Vaucher |
| A delta-sigma modulator has a first summing point subtracting a first feedback signal from an input signal and forwarding a result to a transfer function, a second summing point adding an output signal from said transfer function to the input signal and subtracting a second feedback signal, a first integrator receiving an output signal from the second summing point, a quantizer receiving an output signal from the integrator and generating an output bitstream, and a digital-to-analog converter receiving the bitstream, wherein the first and second feedback signal are the output signal from said digital-to-analog converter delayed by a one sample delay. | ||||||
| 237 | SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND COMPUTER PROGRAM | US14534592 | 2014-11-06 | US20150142455A1 | 2015-05-21 | YUUKI MATSUMURA; SHIRO SUZUKI |
| There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by ΣΔ modulation and a second modulated signal obtained by subjecting the input signal to the ΣΔ modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion. | ||||||
| 238 | Technique for excess loop delay compensation in delta-sigma modulators | US14038350 | 2013-09-26 | US09035813B2 | 2015-05-19 | Eeshan Miglani |
| A technique for excess loop delay compensation in delta sigma modulator. The delta sigma modulator includes a loop filter. The loop filter receives an analog input signal and an output of a digital to analog converter. A comparator receives an output of the loop filter and generates a digital output signal. A reference select logic unit receives the digital output signal as a feedback and generates one or more switching signals. One or more switches are coupled to the comparator and each switch receives a pre-computed reference voltage. The one or more switches are activated by the one or more switching signals in response to the digital output signal. | ||||||
| 239 | Continuous-time delta sigma modulator | US14260899 | 2014-04-24 | US09024795B2 | 2015-05-05 | David Muthers |
| A continuous-time delta sigma modulator, having an integrator and a comparator clocked with a clock frequency that are connected in a feedback loop, having a voltage source that is connected to the comparator for applying a threshold voltage to the comparator, in which an integration time constant of the integrator has a first resistor and a first capacitor, in which the voltage source has a second resistor and a second capacitor for setting the threshold voltage, in which the first resistor and the second resistor are part of a resistor pairing structure, and in which the first capacitor and the second capacitor are part of a capacitor pairing structure. | ||||||
| 240 | Sigma-delta modulators with high speed feed-forward architecture | US14097451 | 2013-12-05 | US09019136B2 | 2015-04-28 | Chen-Yen Ho; Hung-Chieh Tsai; Yu-Hsin Lin |
| A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands. | ||||||
QQ群二维码
意见反馈
意见反馈