| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Apparatus for oscillator with improved precision and associated methods | US15238525 | 2016-08-16 | US09966900B2 | 2018-05-08 | Marty Pflum; Arup Mukherji; John M. Khoury |
| An apparatus includes a first oscillator to generate an output signal that has a first frequency. The apparatus further includes a second oscillator to generate an output signal that has a second frequency. The second frequency varies as a function of temperature. The apparatus further includes a controller that counts a number of cycles of the output signal of the second oscillator in order to determine whether to calibrate the first oscillator. | ||||||
| 182 | Apparatus for Oscillator with Improved Precision and Associated Methods | US15238525 | 2016-08-16 | US20180054162A1 | 2018-02-22 | Marty Pflum; Arup Mukherji; John M. Khoury |
| An apparatus includes a first oscillator to generate an output signal that has a first frequency. The apparatus further includes a second oscillator to generate an output signal that has a second frequency. The second frequency varies as a function of temperature. The apparatus further includes a controller that counts a number of cycles of the output signal of the second oscillator in order to determine whether to calibrate the first oscillator. | ||||||
| 183 | Motor drive voltage control device and method for controlling motor drive voltage | US15293838 | 2016-10-14 | US09882523B2 | 2018-01-30 | Junichi Urata; Masayuki Inaba |
| To suppress a decline in the control accuracy of an applied voltage associated with an increase in quantum noise, and to increase the control accuracy of a motor speed. When generating a driving voltage signal supplied to a motor from a driving command signal, a motor-driving voltage control device reduces the gradation level and performs noise-shaping modulation before performing PWM modulation. Reducing the gradation level allows the degree of gradation of the driving voltage signal to be within the resolution range of the PWM modulation, and thus PWM modulation can be performed even when the driving voltage signal has a high frequency. Noise-shaping modulation reduces the level of quantum noise near the low frequency range by causing the quantum noise due to digitization, included in the driving voltage signal, to be biased toward the high frequency range side. Of modulation signals with the reduced-gradation level, the components near the high frequency band are cut, while the components near the low frequency range are used to suppress quantum noise and control the driving voltage applied to the motor with a high accuracy. | ||||||
| 184 | Delta-sigma modulator with delta-sigma truncator and associated method for reducing leakage errors of delta-sigma modulator | US15647253 | 2017-07-11 | US09859914B1 | 2018-01-02 | Chan-Hsiang Weng; Tien-Yu Lo |
| A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal. | ||||||
| 185 | Low frequency precision oscillator | US14978837 | 2015-12-22 | US09823687B2 | 2017-11-21 | Arup Mukherji; John M. Khoury |
| A technique includes using a first oscillator to clock operations of a radio of an integrated circuit (IC). The technique includes intermittently using the first oscillator to frequency tune a second oscillator of the IC. | ||||||
| 186 | DIRECT DIGITAL SYNTHESIS OF SIGNALS USING MAXIMUM LIKELIHOOD BIT-STREAM ENCODING | US15495635 | 2017-04-24 | US20170293485A1 | 2017-10-12 | Kameran Azadet; Steven C. Pinault |
| Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal. | ||||||
| 187 | Direct digital synthesis of signals using maximum likelihood bit-stream encoding | US15187651 | 2016-06-20 | US09760338B2 | 2017-09-12 | Kameran Azadet |
| Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal. | ||||||
| 188 | Delta Sigma Modulator with Dynamic Error Cancellation | US15489124 | 2017-04-17 | US20170222658A1 | 2017-08-03 | Eeshan Miglani; Karthikeyan Gunasekaran; Santhosh Kumar Gowdhaman; Shagun Dusad |
| The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals. | ||||||
| 189 | Signal processing device and communication device | US15307044 | 2015-01-28 | US09698816B2 | 2017-07-04 | Takashi Maehata |
| Reduction in signal intensity of a harmonic component included in an output of a delta-sigma modulator is suppressed. A signal processing device includes: a delta-sigma modulator 11 that outputs a pulse signal; a first processor 12 that generates, from the pulse signal PO outputted from the delta-sigma modulator 11, a discontinuous pulse signal PC in which each of one-pulse sections in the pulse signal PO has a low level region on at least one of a rear end and a front end of the one-pulse section; and a second processor that generates a short-width pulse signal PS having a pulse width shorter than a pulse width of the discontinuous pulse signal PC generated by the first processor 12. | ||||||
| 190 | Sigma-delta modulator for generating a sinusoidal signal | US15072837 | 2016-03-17 | US09692445B1 | 2017-06-27 | Brent Peterson; Joonsung Park; Krishnaswamy Nagaraj; Tyler Witt |
| A system includes a storage device containing machine instructions and a plurality of digital values of an oversampled sinuisoidal signal. The system also includes a core coupled to the storage. The core is configured to execute the machine instructions, wherein, when executed, the machine instructions cause the core to implement a sigma-delta modulator that retrieves the plurality of digital values from the storage device as input to the modulator. The sigma-delta modulator is configured compute an output bit stream. The system further includes an analog filter configured to receive the output bit stream from the core and to low-pass filter the output bit stream to produce a sinusoidal output signal. | ||||||
| 191 | CIRCUIT AND METHOD FOR CONVERTING ANALOG SIGNAL TO DIGITAL VALUE REPRESENTATION | US15369777 | 2016-12-05 | US20170179976A1 | 2017-06-22 | Jan Craninckx; Jonathan Borremans; Maarten De Bock |
| A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement. | ||||||
| 192 | LOW FREQUENCY PRECISION OSCILLATOR | US14978837 | 2015-12-22 | US20170177020A1 | 2017-06-22 | ARUP MUKHERJI; JOHN M. KHOURY |
| A technique includes using a first oscillator to clock operations of a radio of an integrated circuit (IC). The technique includes intermittently using the first oscillator to frequency tune a second oscillator of the IC. | ||||||
| 193 | Delta sigma modulator with dynamic error cancellation | US15226436 | 2016-08-02 | US09660665B2 | 2017-05-23 | Eeshan Miglani; Karthikeyan Gunasekaran; Santhosh Kumar Gowdhaman; Shagun Dusad |
| The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals. | ||||||
| 194 | Direct digital synthesis of signals using maximum likelihood bit-stream encoding | US14944184 | 2015-11-17 | US09632750B2 | 2017-04-25 | Kameran Azadet; Steven C. Pinault |
| Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal. | ||||||
| 195 | Combined RF equalizer and I/Q imbalance correction | US13661355 | 2012-10-26 | US09612794B2 | 2017-04-04 | Kameran Azadet; Joseph H. Othmer; Meng-Lin Yu |
| Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal. | ||||||
| 196 | Digital architecture for delta-sigma RMS-to-DC converter | US14999288 | 2016-04-21 | US09575729B1 | 2017-02-21 | Djuro G. Zrilic |
| Disclosed is a completely digital solution for a new type of root-mean-square to direct current conversion (RMS-to-DC) apparatus. The design is based on delta-sigma modulation (Δ-ΣM) and the direct nonlinear processing of the Δ-Σ modulated pulse stream. The only external component of the integrated circuit (IC) is capacitor C. The disclosed apparatus consists of low power consuming components which are simple, reliable and inexpensive. | ||||||
| 197 | Digital to analog converter circuits, apparatus and method for generating a high frequency transmission signal and methods of digital to analog conversion | US14835031 | 2015-08-25 | US09571120B2 | 2017-02-14 | Franz Kuttner; Antonio Passamani; Davide Ponton |
| A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval. | ||||||
| 198 | Single amplifer bi-quad sigma-delta modulator | US14977341 | 2015-12-21 | US09559719B1 | 2017-01-31 | John G. Kauffman; Udo Schuetz |
| Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier, a quantizer coupled to the output node of the amplifier, and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier. | ||||||
| 199 | LOW POWER ANALOG TO DIGITAL CONVERTER | US15265730 | 2016-09-14 | US20170005670A1 | 2017-01-05 | Takao Oshita; George L. Geannopoulos; David E. Duarte; J. Keith Hodgson; James S. Ayers; Avner Kornfeld; Jonathan P. Douglas |
| Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal. | ||||||
| 200 | APPARATUS FOR CORRECTING LINEARITY OF A DIGITAL-TO-ANALOG CONVERTER | US14736155 | 2015-06-10 | US20160365867A1 | 2016-12-15 | John G. Kauffman; Udo Schuetz |
| Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell. | ||||||
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