| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 261 | DELTA-SIGMA A/D CONVERTER | US13523592 | 2012-06-14 | US20130057419A1 | 2013-03-07 | Takashi MATSUMOTO; Toshio KUMAMOTO; Takashi OKUDA |
| A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer. | ||||||
| 262 | Synthesis Method Of Sigma-delta Modulator Capable Of Relaxing Circuit Specification And Reducing Power | US13429020 | 2012-03-23 | US20130050000A1 | 2013-02-28 | Shuenn-Yuh LEE; Jia-Hua HONG; Jing-Yi WONG |
| A synthesis method of Sigma-Delta modulator capable of relaxing circuit specification and reducing power consumption, comprising the following steps: firstly, set a target bandwidth and a target performance; upon obtaining a Noise Transfer Function (NTF), perform coefficient synthesis a first time, to ascertain a plurality sets of first performance results corresponding to said NTF, and obtain a plurality sets of first circuit specifications fulfilling said said target performance, through analyzing circuit non-ideal effect of said first performance results. Next, increase an oversampling ratio of parameters, to obtain a plurality sets of second performance results, and a plurality sets of second circuit specifications. Then, increase quantizer bit number, and increase attenuation quantity, to obtain a plurality sets of third circuit specifications. Finally, compare said first, second and third circuit specifications, to select one of greatest variation to perform calibrations. | ||||||
| 263 | Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method | US13072797 | 2011-03-28 | US08344921B2 | 2013-01-01 | Yu-Hsin Lin; Hung-Chieh Tsai; Sheng-Jui Huang |
| A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration. | ||||||
| 264 | Conversion of a discrete time quantized signal into a continuous time, continuously variable signal | US13400019 | 2012-02-17 | US08294605B1 | 2012-10-23 | Christopher Pagnanelli |
| Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank. | ||||||
| 265 | ANALOG-TO-DIGITAL CONVERSION APPARATUS AND SIGNAL PROCESSING SYSTEM | US13352615 | 2012-01-18 | US20120194371A1 | 2012-08-02 | Atsumi Niwa; Yosuke Ueno |
| An AD conversion apparatus includes: a first AD converter for converting an input analog signal into a first digital signal; a second AD converter for converting an analog signal obtained as a result of multiplying the input analog signal by a coefficient α into a second digital signal; a first computing unit for multiplying the first digital signal output by the first AD converter by α2 obtained as a result of squaring the coefficient α; a second computing unit for multiplying the second digital signal output by the second AD converter by α−1 which is the reciprocal of the coefficient α; and a third computing unit for computing a difference between a first computation result output by the first computing unit and a second computation result output by the second computing unit and outputting the difference as a result of AD conversion carried out on the input analog signal. | ||||||
| 266 | SIGMA-DELTA CONVERTER SYSTEM AND METHOD | US13305607 | 2011-11-28 | US20120194370A1 | 2012-08-02 | Giri NK Rangan; Roger Levinson; John M. Caruso |
| A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included. | ||||||
| 267 | Reset mode indication for an integrated circuit using a non-dedicated pin | US11361209 | 2006-02-24 | US07345514B2 | 2008-03-18 | Bruce Duewer |
| An integrated circuit has circuitry and pins coupled to the circuitry. One of the pins is an internal reference voltage pin having a pin signal that is set at a level outside of a normal range for the pin signal so that the integrated circuit is indicated to reset and wherein the internal reference voltage pin is normally used by the integrated circuit for internally generating a reference voltage. | ||||||
| 268 | Data converters for programmable logic | US11469862 | 2006-09-03 | US07321327B1 | 2008-01-22 | Tony San; Jinyan Zhang |
| Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation. | ||||||
| 269 | Error averaging comparator based switch capacitor circuit and method thereof | US11277942 | 2006-03-29 | US07242331B1 | 2007-07-10 | Chia-Liang Lin |
| An error averaging comparator based switch capacitor (CBSC) circuit cyclically operates through a sampling phase, a first transfer phase, and a second transfer phase. During the sampling phase, an input voltage is sampled. During the first transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to a first load. During the second transfer phase, the sampled input voltage is amplified by the same fixed ratio and transferred to a second load. The circuit configuration during the second transfer phase is substantially the same as that during the first transfer phase, except that the at least one of its circuit elements is connected in a reverse polarity. Due to the reverse polarity, the respective errors due to circuit non-idealities during the two transfer phases are exactly opposite. By combining the outputs taken at the first load and at the second load, the errors are averaged out. | ||||||
| 270 | Signal Processing Unit and Method for Time of Flight Measurement | US15727376 | 2017-10-06 | US20190107608A1 | 2019-04-11 | Paul Ta |
| A signal processing unit for time of flight measurement includes an oscillation module, a transmission module, a detection module, a multiplier, an analog-to-digital-converter and a processing module. The oscillation module provides m reference phases. The transmission module generates a set of light impulses based on a selection phase selected out of the m reference phases. The detection module receives a set of reflections of the set of light impulses and to generate a detector signal based on the set of reflections. The multiplier obtains a result of a multiplication of the detector signal by a comparison phase. The analog-to-digital-converter converts the result of the multiplier into a digital signal. The processing module determines the comparison phase or the selection phase and calculates an approximate phase difference between the set of generated light impulses and the set of received reflections based on the digital signal. | ||||||
| 271 | Wireless access system and control method for same | US15569802 | 2016-03-07 | US10143041B2 | 2018-11-27 | Shinichi Hori; Tomoyuki Yamase |
| Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal. The remote unit (3) includes: a local generation unit (10) that extracts the clock signal from the 1-bit signal output from the center unit (1), and generates a local signal using the extracted clock signal as a reference signal; a filter (13) that extracts a desired band component from the 1-bit signal; and an up-converter (14) that converts, using the local signal, an output signal of the filter into a high-frequency signal. | ||||||
| 272 | Signal phase tracking with high resolution, wide bandwidth and low phase noise using compound phase locked loop | US15934890 | 2018-03-23 | US10122527B1 | 2018-11-06 | Gerald R. Fischer |
| A clock recovery circuit for providing clock recovery from a burst signal that is periodically present and absent in a noisy channel. The recovery circuit includes an outer main tracking second-order phase locked loop (PLL) having an analog phase detector, a digital loop filter, and an analog/digital hybrid numerically controlled oscillator (NCO) that operates so that the clock recovery frequency is “frozen” to its last value from the previous burst and the phase detector is disabled during the gaps between data bursts. The NCO is implemented with an inner loop PLL that operates as a high resolution synthesizer having a low internal control bandwidth that preserves VCO phase noise. The outer main loop achieves a higher control bandwidth through direct tuning of the inner loop VCO with the outer loop tuning signal. | ||||||
| 273 | RADIO FREQUENCY AMPLIFIER | US15520378 | 2015-10-20 | US20180302048A1 | 2018-10-18 | Bryan James DONOGHUE; Desmond PHILLIPS; Tan ROBERT; Peter-Contesse HERVE |
| A modulator circuit includes a plurality of signal processing branches, each branch having a modulator for performing a delta-sigma modulation of a respective data stream portion in order to generate a modulated signal. The modulator circuit receives an input data stream having a carrier frequency; splits the input data stream into a plurality of data stream portions. Delta-sigma modulation is performed in each branch on a respective data stream portion. The respective modulated signals from each branch are combined to form an output signal for outputting at the carrier frequency. | ||||||
| 274 | WIRELESS ACCESS SYSTEM AND CONTROL METHOD FOR SAME | US15569802 | 2016-03-07 | US20180139802A1 | 2018-05-17 | Shinichi HORI; Tomoyuki YAMASE |
| Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal. The remote unit (3) includes: a local generation unit (10) that extracts the clock signal from the 1-bit signal output from the center unit (1), and generates a local signal using the extracted clock signal as a reference signal; a filter (13) that extracts a desired band component from the 1-bit signal; and an up-converter (14) that converts, using the local signal, an output signal of the filter into a high-frequency signal. | ||||||
| 275 | Delta sigma modulator with dynamic error cancellation | US15489124 | 2017-04-17 | US09853657B2 | 2017-12-26 | Eeshan Miglani; Karthikeyan Gunasekaran; Santhosh Kumar Gowdhaman; Shagun Dusad |
| The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals. | ||||||
| 276 | Circuit and method for converting analog signal to digital value representation | US15369777 | 2016-12-05 | US09806737B2 | 2017-10-31 | Jan Craninckx; Jonathan Borremans; Maarten De Bock |
| A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement. | ||||||
| 277 | All-optical proteretic photonic integrated device | US15200104 | 2016-07-01 | US09806697B2 | 2017-10-31 | Mohammad R. Sayeh; Nima Davoudzadeh Mahboub Sedigh; Mohamad Tafazoli Mehrjerdi |
| An apparatus and a method for a design and a simulation of an all-optical proteretic bi-stable device. The proteresis is a reversed hysteresis with an interesting characteristic which increases the oscillation frequency of a feed-back system with a relaxation dynamics by reducing the feed-back delay. The calculation of the bi-stable device parameters, a simulation of the theoretical device, and a simulation of the all-optical device are given. Applications of the proteretic device in ultra-high speed oscillations are also disclosed. | ||||||
| 278 | Software digital front end (SoftDFE) signal processing | US13701374 | 2012-10-26 | US09778902B2 | 2017-10-03 | Kameran Azadet; Chengzhou Li; Albert Molina; Joseph H. Othmer; Steven C. Pinault; Meng-Lin Yu; Joseph Williams; Ramon Sanchez Perez; Jian-Guo Chen |
| Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction. | ||||||
| 279 | Receiver for simultaneous signals in carrier aggregation | US14931665 | 2015-11-03 | US09768797B2 | 2017-09-19 | Chadi Jabbour; Seyed Majid Homayouni; Sudhir Aggarwal; Vason P. Srini |
| Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port providing at least a first carrier aggregation signal and a second carrier aggregation signal; and a quadrature phase sigma delta receiver coupled to the radio frequency input port providing at least the first carrier aggregation signal and the second aggregation signal, wherein the in-phase sigma delta receiver and the quadrature phase sigma delta receiver each include a resonator stage circuitry including at least one variable capacitor that varies notch frequencies to provide passbands for the first carrier aggregation signal and the second carrier aggregation signal. Related apparatus, systems, methods, and articles are also described. | ||||||
| 280 | Built-in-self-test circuit for sigma-delta modulator | US15365947 | 2016-12-01 | US09748970B1 | 2017-08-29 | Zhou Fang; Song Huang; Chao Liang; Yifeng Liu; Wanggen Zhang |
| A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison. | ||||||
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