Feedforward delta-sigma modulator |
|||||||
申请号 | US14332396 | 申请日 | 2014-07-16 | 公开(公告)号 | US09035814B2 | 公开(公告)日 | 2015-05-19 |
申请人 | Realtek Semiconductor Corp.; | 发明人 | Che-Wei Chang; | ||||
摘要 | A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder. | ||||||
权利要求 | What is claimed is: |
||||||
说明书全文 | 1. Field of the Invention The present invention relates to a feedforward delta-sigma modulator, and particularly to a feedforward delta-sigma modulator that can implement an adder function required by the feedforward delta-sigma modulator in a charge domain. 2. Description of the Prior Art When a feedforward delta-sigma modulator implements an adder function in a voltage domain, the feedforward delta-sigma modulator increases power consumption due to utilizing additional operational amplifiers. In addition, because limited bandwidth of the additional operational amplifiers can cause excess loop delay (ELD), performance of the feedforward delta-sigma modulator is decreased. When a feedforward delta-sigma modulator implements an adder function in a current domain, chip area, power consumption, and complexity of the feedforward delta-sigma modulator are increased because transconductance units of the feedforward delta-sigma modulator need enough linearity to maintain linearity of the feedforward delta-sigma modulator. When a feedforward delta-sigma modulator utilizes ratios of feedforward capacitors to an integrating capacitor of a last stage integrator to implement feedforward coefficients, the feedforward capacitors become larger with the integrating capacitor because the integrating capacitor is usually very large to meet a low noise requirement, resulting in the feedforward delta-sigma modulator needing larger chip area. In addition, the feedforward capacitors can also increase power consumption of operational amplifiers of the feedforward delta-sigma modulator. Another feedforward delta-sigma modulator utilizes a multi-input comparator to directly connect all feedforward paths, wherein size ratios of input transistors of the feedforward delta-sigma modulator are used for implementing feedforward coefficients. However, a disadvantage of the feedforward delta-sigma modulator with the multi-input comparator is that each feedforward coefficient is sensitive to a common mode voltage of a corresponding integrator output terminal, so large offsets exist between feedforward coefficients of the feedforward delta-sigma modulator when common mode output voltages of integrators of the feedforward delta-sigma modulator are inconsistent. In addition, because delay time of a quantizer and an analog-to-digital converter can decrease performance of delta-sigma modulator, and even make loop of the delta-sigma modulator unstable, the prior art utilizes an additional digital-to-analog converter between an input terminal of the quantizer and an output terminal of the delta-sigma modulator to compensate the delay time. However, the additional digital-to-analog converter can increase chip area and power consumption of the delta-sigma modulator. Therefore, the above mentioned feedforward delta-sigma modulators provided by the prior art are not good enough choices for a user. In view of the above mentioned problems of the prior art, the present invention provides a feedforward delta-sigma modulator. The feedforward delta-sigma modulator implements an adder function required by the feedforward delta-sigma modulator in a charge domain to solve the above mentioned problems of the prior art. An embodiment provides a feedforward delta-sigma modulator. The feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit. The successive approximation analog-to-digital converter includes N+1 input terminals, and an output terminal for outputting a digital signal, wherein an input terminal of the N+1 input terminals is used for receiving an analog input signal, and N is a positive integer. The digital-to-analog converter is coupled to the output terminal of the successive approximation analog-to-digital converter for receiving the digital signal, and generating an analog feedback signal accordingly. An output terminal of each integrator of the N integrators is coupled to a corresponding input terminal of the N+1 input terminals. The first adder is coupled to the digital-to-analog converter for summing the analog input signal and the analog feedback signal to a first integrator of the N integrators. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, wherein an output terminal of the Kth integrator is coupled to an input terminal of a (K+1)th integrator of the N integrators, and K is a positive integer less than N. The optimization zero generation unit is coupled between the second adder and an output terminal of the (K+1)th integrator. Compared to the prior art, the present invention has advantages as follows: first, the present invention implements an adder function required by the feedforward delta-sigma modulator in a charge domain, so in a preferred embodiment of the present invention does not need additional operational amplifiers and transconductance amplifiers, resulting in the present invention having smaller chip area, lower power consumption, and lower complexity; second, capacitances of sampling capacitors of the feedforward delta-sigma modulator only correspond to a capacitance of a reference capacitor (that is, the capacitances of the sampling capacitor are only proportional to the capacitance of the reference capacitor) and unrelated to integrating capacitors within integrators of the feedforward delta-sigma modulator, so the capacitances of the sampling capacitors can be very small, resulting in power consumption of operational amplifiers within the integrators of the feedforward delta-sigma modulator being reduced; third, the present invention is insensitivity to a common mode voltage outputted by each integrator, an output voltage of each integrator, and an amplitude of an analog input signal, so the present invention is suitable for high speed, high resolution , and low power consumption applications. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. Please refer to Please refer to Please refer to During a sampling signal Φs, the common mode switch 1034 receives a common mode switch signal Φsa, so the common mode switch 1034 is turned on, resulting in second terminals of the sampling capacitors f1C-f4C and a second terminal of the reference capacitor Cr receive the common mode voltage of the common mode terminal CT. That is, the second terminals of the sampling capacitors f1C-f4C and the second terminal of the reference capacitor Cr are reset. When the 4 switch units 10221-10224 receive the sampling signal Φs (a sampling period as shown in When the 4 switch units 10221-10224 receive a holding signal Oh (a holding period as shown in After the control signal ΦL2 is generated, the successive approximation logic control unit 1036 can generate the strobe signal SS to drive the comparator 1032 and generate control signals ΦL3, ΦL4, ΦL5, . . . to the reference voltage switching unit 1030 according to the clock CK, so the reference voltage switching unit 1030 can switch the first terminal of the reference capacitor Cr to receive a corresponding reference voltage of the plurality of reference voltages generated by the reference voltage generation unit 1028 according to the control signals ΦL3, ΦL4, ΦL5, . . . . Therefore, when the first terminal of the reference capacitor Cr is switched to receive a corresponding reference voltage of the plurality of reference voltages generated by the reference voltage generation unit 1028 every time, the charges of the second terminal of the reference capacitor Cr and the charges of the second terminals of the sampling capacitors f1C-f4C can be redistributed to generate a corresponding voltage. Meanwhile, the comparator 1032 can complete traditional successive approximation analog-to-digital conversion according to the corresponding voltage and the common mode voltage of the common mode terminal CT. In addition, the above mentioned embodiment only utilizes single-ended operation to describe the present invention. That is, the present invention is not limited to single-ended operation or differential operation. To sum up, compared to the prior art, the feedforward delta-sigma modulator provided by the present invention has advantages as follows: first, the present invention implements an adder function required by the feedforward delta-sigma modulator in a charge domain, so in a preferred embodiment of the present invention does not need additional operational amplifiers and transconductance amplifiers, resulting in the present invention having smaller chip area, lower power consumption, and lower complexity; second, the capacitances of the sampling capacitors of the feedforward delta-sigma modulator only correspond to the capacitance of the reference capacitor (that is, the capacitances of the sampling capacitor are only proportional to the capacitance of the reference capacitor) and unrelated to integrating capacitors within the integrators, so the capacitances of the sampling capacitors can be very small, resulting in power consumption of the operational amplifiers within the integrator being reduced; third, the present invention is insensitivity to a common mode voltage outputted by each integrator, an output voltage of each integrator, and an amplitude of an analog input signal, so the present invention is suitable for high speed, high resolution , and low power consumption applications. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. |