Fractional divider using a calibrated digital-to-time converter专利检索- .校正或测试专利检索查询-专利查询网

Fractional divider using a calibrated digital-to-time converter
申请号	US15479499	申请日	2017-04-05	公开(公告)号	US09897976B2	公开(公告)日	2018-02-20
申请人	Integrated Device Technology, Inc.;			发明人	Song Gao; Brian Buell; Katherine T. Blinick;
摘要	An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.
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