| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | JPS6030131B2 - | JP3851580 | 1980-03-26 | JPS6030131B2 | 1985-07-15 | CHIKAMORI KUNIO |
| 122 | Ratio operator | JP17226383 | 1983-09-20 | JPS6065382A | 1985-04-15 | HIRANO SHIGENORI |
| PURPOSE:To obtain a ratio operator having high stability with a simple circuit by supplying an analog signal V1 and an analog signal V2 to an analog input terminal and a reference voltage terminal of a D/A converting circuit respectively to obtain an output V1/V2 in the form of the digital value. CONSTITUTION:For a feedback comparison type A/D converter 10, the reference voltage Vr is supplied to a reference voltage terminal S of a D/A converting circuit 14. Then an analog input V1 is fed to an analog input terminal A to start the converter 10. Then the input V1 is converted into the digital value every prescribed conversion cycle and delivered through a register 12. These digital outputs B0...Bi can be regarded as a ratio V1/Vr. Then an analog signal V2 is supplied to the terminal S in place of the voltage Vr to obtain an output equal to the value of V1/Vr. Therefore the ratio V1/V2 between two analog signals is obtained as the digital value. | ||||||
| 123 | Convolution processor | JP14156784 | 1984-07-10 | JPS6051314A | 1985-03-22 | NINGU SHINGU RUU |
| 124 | Voltage generator | JP17509782 | 1982-10-04 | JPS5963577A | 1984-04-11 | YAMAGUCHI HIDEHIKO |
| PURPOSE:To remove an offset voltage, and to reduce the number of D-A converters to only one set for every voltage generating circuit, and to reduce the cost by varying an offset bias which is in a digital signal state. CONSTITUTION:A data converter 201 which performs addition and subtraction according to polarity data is provided, and a digital signal corresponding to the most significant digit bit value of set data 102 is applied as the offset bias by this data setter 201; set voltage data is added on the positive polarity side based upon the bias or subtracted on the negative polarity side, thus performing data conversion. The adding operation and subtracting operation of this data converter 201 are switched according to the polarity data stored in a polarity data register 107 and the arithmetic result is supplied to a D-A converter 202; the converter 202 has a normal output terminal 202a and a complement output terminal 202b, and a current-voltage converter 104 is connected to the normal output terminal 202a to obtain a plus analog voltage. Further, the current-voltage converter 104' consisting of a resistor 203 is connected to the complement output terminal 202b to obtain an analog voltage in negative polarity. | ||||||
| 125 | Hybrid computer | JP11413183 | 1983-06-24 | JPS5957375A | 1984-04-02 | PIITAA JII BAATORETSUTO |
| 126 | Switch using highly accurate rate multiplier for transmitter | JP12114083 | 1983-07-05 | JPS5941059A | 1984-03-07 | MARION EI KIIZU FUOOSU; UIRIAMU ERU TOMUPUSON |
| 127 | Interpolative function generator for determining root for transmitter | JP12706583 | 1983-07-14 | JPS5927347A | 1984-02-13 | CHIETSUTO JIEI SURABINSUKI |
| 128 | JPS596395B2 - | JP14996477 | 1977-12-15 | JPS596395B2 | 1984-02-10 | KENESU ROBUSON BURAUN |
| 129 | Signal converting circuit | JP13020382 | 1982-07-26 | JPS5921124A | 1984-02-03 | SUZUKI TADAO; AKAGIRI KENZOU; NISHIGUCHI MASAYUKI |
| PURPOSE:To reduce the noise modulation as well as the increase of noises and distortions due to the compression/expansion of amplitude, by providing the amplitude dependence characteristics to the input/output characteristics of a signal converting circuit. CONSTITUTION:A transmitted digital signal Dx is converted into Dx by a converting circuit 7 and applied to a digital input terminal of a D/A converter 4. While a signal (x) obtained by converting the signal Dx into an analog signal by a D/A converter 6 is supplied to a multiplication terminal K of the converter 4 through a converting circuit 8 and an adder 9. The signal (x) is delivered in the form of a squared expansion output x<2> after a gain control done by a digital input. At the same time, the output x<2> is applied with adverse polarity to an adder 9 through a transmitting circuit 10. Thus a negative feedback loop is formed to the input from the output of the adder 9. In such constitution, the feedback quantity is increased for the input of a high level. Therefore no substantial multiplication is carried out any more. Thus it is possible to obtain the expansion characteristics corresponding to an input level. | ||||||
| 130 | Signal processing circuit | JP12843782 | 1982-07-23 | JPS5919428A | 1984-01-31 | SUZUKI TADAO; AKAGIRI KENZOU; NISHIGUCHI MASAYUKI |
| PURPOSE:To reduce noise modulation and to decrease the increase in noise and in distortion produced as the amplitude is compressed and expanded, by providing a frequency dependancy to an output of the 2nd D/A converting circuit and giving it to the 1st D/A converting circuit. CONSTITUTION:An input digital signal DX is given to the 1st D/A converting circuit 4 and also to the 1st converting circuit 7 functioning as an absolute value circuit. Further, a signal converted into an absolute value at the 1st converting circuit 7 is inputted to the 2nd D/A converting circuit, where the signal is converted into an analog signal, and the signal passes through the 2nd converting circuit 8 having frequency characteristics such as a high-frequency emphasis (low-frequency demphasis) circuit, is given to a multiplication terminal K of the 1st A/D converting circuit 4 so as to obtain the analog signal controlling the input digital information relating to the amplitude axis from the 1st D/A converting circuit. Thus, the noise modulation produced by the fact that the noise at a high frequency is subjected to the amplitude modulation with a low frequency component can be reduced. | ||||||
| 131 | Analog signal processing device | JP13378781 | 1981-08-26 | JPS5835671A | 1983-03-02 | YAMANE MASANORI; NARABA KEIZOU |
| PURPOSE:To make parts such as a variable resistor unnecessary to improve the reliability of the device, by performing the comparison for the zero level and the span level in a reference voltage and current generator and a comparator adjust A/D and D/A converters by the data processing device. CONSTITUTION:The output terminal of a D/A converter 5 having a data storage circuit 8 is connected to a voltage comparator 6 and an A/D converter 2 having a data storage circuit 7. A data processing device 3 is connected to the input side of the converter 5, and the digital signal from the device 3 is converted to an analog signal. The output of a reference voltage and current generator 1 is applied to the comparator 6, and the output of the generator 1 and the analog output from the converter 5 are compared operated in this comparator 6, and the operation result is applied to the device 3. Until the output signal indicating the coincidence detection is obtained from the comparator 6 in the device 3 in respect to the zero level and the span level, the digital output is fed back and is outputted as correction data to devices 7 and 8. By this constitution, a variable resistance or the like is unnecessary, and the reliability of the processing device is improved. | ||||||
| 132 | Multiplying device | JP12486881 | 1981-08-10 | JPS5827271A | 1983-02-17 | WATANABE KOUJIROU |
| PURPOSE:To complete one multiplication of complex numbers within the reference time of a memory by regarding a maltiplic and expressed by a binary number as an address in an ROM and writing the real and imaginary number parts of the multiplied result to the corresponding content of the ROM. CONSTITUTION:A register 1 stores An-k information encoded into a binary number so as to assign a number to the information. An analog/digital (A/D) converter 2 converts the real number part of an error Yn-An outputted from a receiver into digital information. In the same manner an A/D converter 3 converts the imaginary number part of the Yn-An into digital information. Outputs of 9 bits in total from the register 1, the A/D converter 2 and the A/D converter 3 are inputted to the address of an ROM4. The ROM4 has 2N outputs and the N outputs and the remaining N outputs correspond to the real number and imaginary number of a multiplied result respectively and are displayed as binary numbers. By said procedure, A/D conversion of about 3 bits can be maintained at the accuracy of abuut 6 bits for a signal level. | ||||||
| 133 | Average value operating device | JP10938581 | 1981-07-15 | JPS5812071A | 1983-01-24 | TANI YUKIZUMI |
| PURPOSE:To obtain a highly accurate operating device, by providing a function selecting a register inputted with the number of times of sampling for a circuit which A/D-converts an instantaneous value of an analog quantity, D/A-converts data of the register and obtains an average value. CONSTITUTION:A value x1 converted from an input analog quantity into a digital quantity at an A/D converter 1, passes through a switch 81 controlled at a control section 7, and is inputted to a register R1. A nect data x2 passes through 81', is inputted to R1' and the operation of 1/2(x1+x2) is made at an operation device 91, the result is inputted to a register R2 and the switch 81 resets the R1. The next input data passes through the switch 81 and is inputted to the R1. Similarly, the operation is made up to a register Rk. The output of the R1-Rk is D/A-converted 51-5k into analog quantity. The number of times of sampling is inputted to a counter 10 with the control section 7, converted into the analog quantity at a D/A converter 5k+1 and inputted as a denominator of dividers 111-11k. The output of the dividers is inputted to an adder 12 and the output is an average value. | ||||||
| 134 | JPS5757721B2 - | JP12099176 | 1976-10-08 | JPS5757721B2 | 1982-12-06 | SUMI AKIRA; KATAOKA FUSATOSHI |
| 135 | Signal processing device | JP1487181 | 1981-02-03 | JPS57130178A | 1982-08-12 | KANEDA HIROYUKI |
| PURPOSE:To supplying a signal, which is detected as regular, as a timing signal to a processing circuit, by comparing an input signal and a reference signal with each other. CONSTITUTION:The input signal from a terminal 10 is converted to a digital value by an A/D converting part 20 and is supplied to a comparing circuit 30 and an adding circuit 50, and the circuit 30 generates a control signal 110 to the adding circuit 50, a storage circuit 60, and a counting circuit 70 when the input signal exceeds the reference signal from a reference level generating part 40, and the circuit 50 adds read contents of the circuit 60 and the input signal, and the circuit 60 stores the addition result. The circuit 70 counts the number of times of generation of the control signal on a basis of the command of the circuit 30 to obtain the number of times of addition, and this count value is supplied to a dividing circuit 80. The dividing circuit 80 divides the total after the last addition operation of the circuit 60 by the value of the circuit 70 to calculate an average value of the input signal and outputs it to a terminal 90. | ||||||
| 136 | Differentiator having digital integrating function | JP18035480 | 1980-12-22 | JPS57105081A | 1982-06-30 | NAGAI HIDENORI |
| PURPOSE:To ensure the even accuracy regardless of the level of a input voltage, by providing a digital integrating function by an up-down counter and applying negative feedback to an operational amplifying circuit. CONSTITUTION:Receiving a voltage input signal Vi, an operational amplifying circuit part 2 delivers a voltage output signal Vo'. This voltage Vo' is applied to an absolute value amplifier 3a and a voltage comparator 3d of an integral arithmetic circuit part 3. Thus an output ¦Vo'¦ is obtained from the amplifier 3a and then applied to a voltage frequency converter 3b to obtain an output SF having a pulse frequency proportional to the voltage ¦Vo'¦ through the comparator 3b. On the other hand, the comparator 3d discriminates the plus or minus of the voltage Vo' and applies a control input signal to a counter 3c. The counter 3c performs the up-counting and down-counting for the output SF when the voltage Vo' is plus and minus respectively. The output of the counter 3c is fed back to the circuit part 2 via a D/A converter 3f. As a result, no error is produced although the input voltage is particularly high. | ||||||
| 137 | Average level removing system | JP12398680 | 1980-09-09 | JPS5748663A | 1982-03-20 | KITAMURA SHINICHI |
| PURPOSE:To eliminate the need for a costly high speed A/D converter of multibits and lower the cost of production by obtaining the digital value used for calculation of average values by low speed A/D conversion. CONSTITUTION:The output of a low speed A/D converter 61 inputted with an analog signal (a) is inputted to an average level operating circuit 52 consisting of plural registers and adders, and a digital average signal (b') is latched by latch circuits 63, 64. The digital average signal (f') thereof is again converted to an analog signal (f) by a low speed D/A converter 65, and the difference between the analog signal (f) and the analog signal (a) is amplified by a differential amplifier 66. This signal (g) is converted by a high speed A/D converter 67, by which a digital signal (g') for flaw detection is obtained. Thereby, inexpensive circuits are used and the production cost for the device is lowered. | ||||||
| 138 | JPS5645188B2 - | JP9678273 | 1973-08-30 | JPS5645188B2 | 1981-10-24 | |
| 139 | Analog memory device | JP16062580 | 1980-11-14 | JPS5687298A | 1981-07-15 | TOOMASU HOONATSUKU; JIYON JIEI KOKORAN; SAMIYUERU EICHI MASURATSUKU |
| PURPOSE: To obtain an output with a compensation given to both the gain and offset of an analog memory element, by using a system which combines unadjusted output value obtained from an analog input waveform with the known analog input. CONSTITUTION: The analog signal is led to the analog memory element 11 via the input line 13, and then the signal with a desired delay given as the output of the element 11 plus an extended time axis is delivered via the line 15. The signal of the line 15 is converted into the digital word via the AD converter 17. This digital word is stored in the digital memory elements 23, 25 and 27 each via the digital multiplexer 21 and then into the digital memory elements 31 and 35 via the signal processors 29 and 37 to be supplied finally to the signal processor 37. The output of the memory element 31 is applied to the analog multiplexer 19 via the A/D converter 33. COPYRIGHT: (C)1981,JPO&Japio | ||||||
| 140 | Random-waveform generator | JP13221079 | 1979-10-12 | JPS5656005A | 1981-05-16 | TASHIRO MAKIHIKO; SAKAI YOSHIYUKI |
| PURPOSE:To relieve a continuous burden on a computer by outputting an analog waveform by transferring memory contents, address by address, to a waveform generating circuit after storing a memory with waveform data calculated once. CONSTITUTION:Host computer 1 generates waveform data through arithmetic and this data is stored in memory 4 via transmitting-receiving circuit 2 under the control of microcomputer 3. After supplying waveform generating circuit 5 with various setpoints, a start address, end address, frequency in repetition, gain value, level value, and timer setpoint, microcomputer 3 actuates waveform generation and transfers required data in memory 4 to waveform generating circuit 5 via the bus line at every timer set time to control signal processing on the basis of various setpoints. Therefore, when a periodic function is outputted continuously for a long time, a burden on the computer is relieved. | ||||||
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