Average level removing system专利检索- 混合计算装置专利检索查询-专利查询网

Average level removing system
申请号	JP12398680	申请日	1980-09-09	公开(公告)号	JPS5748663A	公开(公告)日	1982-03-20
申请人	Fujitsu Ltd;			发明人	KITAMURA SHINICHI;
摘要	PURPOSE:To eliminate the need for a costly high speed A/D converter of multibits and lower the cost of production by obtaining the digital value used for calculation of average values by low speed A/D conversion. CONSTITUTION:The output of a low speed A/D converter 61 inputted with an analog signal (a) is inputted to an average level operating circuit 52 consisting of plural registers and adders, and a digital average signal (b') is latched by latch circuits 63, 64. The digital average signal (f') thereof is again converted to an analog signal (f) by a low speed D/A converter 65, and the difference between the analog signal (f) and the analog signal (a) is amplified by a differential amplifier 66. This signal (g) is converted by a high speed A/D converter 67, by which a digital signal (g') for flaw detection is obtained. Thereby, inexpensive circuits are used and the production cost for the device is lowered.
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