| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | A PARALLEL PROCESSOR NETWORK, A PROCESSOR AND A METHOD FOR SOLVING DIFFERENTIAL EQUATIONS IN A PARALLEL PROCESSOR NETWORK | PCT/FI0200370 | 2002-04-30 | WO02088990A3 | 2003-05-01 | LAIHO MIKA; PAASIO ARI; KANANEN ASKO |
| The present invention relates to a parallel processor network, a processor and a method for solving differential equations in a parallel processor network. A parallel processor network includes several processors (processing units) that are arranged in a regular form. A processing unit is coupled with selected processing units. A problem for integrating this kind of a parallel processor network into a chip is the minimization of the physical size and power consumption of the processor. In the parallel processor network of the invention, the couplings are realized with analog multipliers. The sum of analog couplings is converted to a digital quantity that is used to digitally integrate the state(s) of a processing unit. The state(s) are converted to an analog quantity that is used to control the analog multipliers. The invention allows the minimization of the power consumption and physical size of the paralles processor network. | ||||||
| 62 | 多数のフィードバックパスを備えるシグマデルタ二乗差RMS−DCコンバータ | JP2013543347 | 2011-12-08 | JP6085252B2 | 2017-02-22 | グスタボ ライムンド パウロ シルヴァ |
| 63 | Sigma-delta squared difference rms-dc converter with a large number of feedback path | JP2013543347 | 2011-12-08 | JP2014502801A | 2014-02-03 | ライムンド パウロ シルヴァ グスタボ |
| 多数のフィードバックパスを用いるΣΔ二乗差ＲＭＳ−ＤＣコンバータのアーキテクチャが提供される。 二乗化非線形によって処理される量子化誤差のＲＭＳレベルが最小化される種々のトポロジーにおいて、追加のフィードバックパスが安定なΣΔ閉ループ挙動を可能にする。 このようなフィードバックパスとしては、ローパスフィルタリングされ、定数利得のフィードバックパス、ローパス及びハイパスフィルタリングされたパス、又は多数のローパスフィルタリングされたパスが含まれる。 これらは追加のフィードフォワード又はフィードバックパスによって提供される周波数補償を備え、フォワードパスの多数の積分器と組み合わされ得る。 電子的コンフィギュラビリティがこのアーキテクチャの総入力関連ダイナミックレンジ（ＤＲ）を更に拡張し得る。 | ||||||
| 64 | Method and circuit for supplying the interface signals to a plurality of integrated circuit | JP2011028964 | 2011-02-14 | JP5199409B2 | 2013-05-15 | ガーカンウォル・サホタ; メーディ・ハミディ・サニ; ササン・シャーロキニア |
| 65 | Method for multiplying the analog-to-digital conversion simultaneously | JP2000079665 | 2000-03-22 | JP4472096B2 | 2010-06-02 | エル ガマル アバス; シャオ ドン ヤン デイヴィッド; エイ ファウラー ボイド |
| 66 | Sensor module and method for correcting sense output signal therefrom | JP2008065446 | 2008-03-14 | JP2009224949A | 2009-10-01 | FUJIWARA KAZUNORI |
| PROBLEM TO BE SOLVED: To provide a sensor module and a method for correcting a sensed output signal therefrom which deletes a fluctuation component resulting from output variation in a signal processing unit such as a differential amplifier, an A/D converter, etc. prepared in a latter stage of the sensor in the sensor module including various sensors, the differential amplifier, and A/D converter, etc. SOLUTION: A sensed signal output from a sensor element and a reference voltage having a constant voltage level are selectively input to an amplifier, and amplified signals thereof are sequentially output as A/D-converted data by the A/D converter. An average of a predetermined number of A/D-converted data corresponding to the reference voltage is calculated, and a correction value is obtained by subtracting the average value from one of the A/D-converted data corresponding to the reference voltage. Corrected data are obtained by subtracting the correction value from each A/D-converted data corresponding to the sense signal output from the sensor. COPYRIGHT: (C)2010,JPO&INPIT | ||||||
| 67 | Signal combining circuit having two a / d-converter | JP24089399 | 1999-08-27 | JP4276745B2 | 2009-06-10 | 雅也 岸田 |
| 68 | Hybrid digital / analog processing circuit | JP2003522014 | 2002-08-16 | JP4102753B2 | 2008-06-18 | クリストファー トマゾウ，; アリソン バーデット， |
| 69 | Pwm modulation circuit and class d amplifier using the same | JP2004251527 | 2004-08-31 | JP2006074099A | 2006-03-16 | YANAI HIDEO |
| PROBLEM TO BE SOLVED: To provide a PWM modulation circuit capable of preventing increase in a mounting area of a class D amplifier, and a class D amplifier using the PWM modulation circuit. SOLUTION: This PWM modulation circuit uses a step-like wave to apply PWM modulation to an analog baseband signal. A step-like wave generating circuit 14 has a plurality of constant current source circuits 10, a plurality of switches 16, a serial-parallel conversion circuit 19, and output voltage control circuits 12, 13 for converting constant currents to be inputted from the plurality of constant current source circuits 10 into constant voltages of an arbitrary value and outputting the converted voltages. In the PWM modulation circuit, the plurality of switches each switch an ON/OFF state in response to a clock signal to be inputted from the circuit 19, and the circuits 12, 13 convert constant current inputted from the plurality of the circuits 10 connected to the plurality of switches 16 in an ON state into constant voltages of a predetermined ratio to generate a step-like wave. COPYRIGHT: (C)2006,JPO&NCIPI | ||||||
| 70 | Method and system for encoding, how to decrypt conversion and system | JP50062293 | 1992-05-28 | JP3459417B2 | 2003-10-20 | オー． ジョンソン，キース; ダブリュ． フローマー，マイケル |
| 71 | Clock generation circuit | JP23505595 | 1995-09-13 | JP3434627B2 | 2003-08-11 | 敏雄 川▲崎▼ |
| 72 | Dynamic digital synchro converter | JP2000548958 | 1999-04-30 | JP2002515672A | 2002-05-28 | シー． セウエル，ウエズリー; ビー． ニアリー，ウインザー |
| (57)【要約】 ディジタル・シンクロコンバータはディジタル値をアナログシンクロ信号に変換する。 この値はメモリでマッピング処理され、ディジタル・アナログコンバータへ送られて、ディジタル値がアナログ値に変換される。 次に標本保持回路を用いてアナログシンクロ信号が作成される。 | ||||||
| 73 | Digital peak detector and detection method for minimum value and maximum value | JP2000124806 | 2000-04-25 | JP2000329793A | 2000-11-30 | MOSER MICHAEL F |
| PROBLEM TO BE SOLVED: To fetch events with a shorter continuation period in a digital peak detector. SOLUTION: A plurality of fetching means 26 are arranged so as to be able to interleave and a common input signal is supplied. For each fetching interval, each fetching means detects the maximum peak value and the minimum peak value. A microprocessor 20 compares all minimum peak values detected by a plurality of fetching means and obtains the minimum peak value in all, and compares all maximum peak values detected by a plurality of fetching means 26 and obtains the maximum peak value in all. COPYRIGHT: (C)2000,JPO | ||||||
| 74 | Transmission data shaping device | JP32870895 | 1995-12-18 | JP3081957B2 | 2000-08-28 | 賢徳 田尻; 昭宏 西澤 |
| 75 | Signal processor | JP8926299 | 1999-03-30 | JP2000050106A | 2000-02-18 | WATANABE TORU |
| PROBLEM TO BE SOLVED: To stably execute a signal processing in a signal processing circuit where an analog processing circuit and a digital processing circuit coexist. SOLUTION: A complementary data generation circuit 14 outputs digital data D1(n) as main data Da(n) at prescribed timing and auxiliary data Db(n) where the number of change points complementarily changes at the switching timing of data against the main data Da(n). The main data Da(n) and auxiliary data Db(n) are outputted from output circuits 15 and 16 in parallel. Thus, the total consumption current of the output circuits 15 and 16 at the switching timing of data is held to be constant and the fluctuation of power potential is prevented. COPYRIGHT: (C)2000,JPO | ||||||
| 76 | Noise generator | JP1200291 | 1991-02-01 | JP2795545B2 | 1998-09-10 | MURATA YASUKI; YOSHIKAWA SHUICHI; NISHIWAKI HIROSHI |
| 77 | Multiplier using charge transfer devices | JP20025594 | 1994-08-03 | JP2617425B2 | 1997-06-04 | 靖夫 永積 |
| 78 | Semiconductor device, semiconductor circuit using the device, correlation arithmetic device, a/d converter, d/a converter and signal processing system | JP26504194 | 1994-10-28 | JPH08125502A | 1996-05-17 | KOUCHI TETSUNOBU; MIYAWAKI MAMORU |
| PURPOSE: To reduce a circuit scale, to improve arithmetic operation speed, to reduce power consumption, to reduce manufacture cost and to improve manufacture yield in a semiconductor device. CONSTITUTION: In the semiconductor device, a capacity means 2 is connected to a multilple input terminal through a latch means 12. Terminals of either sides of the respective capacity means are connected in common, and signals are inputted to a sense amplifier 5. Input signals inputted from the latch means to an input terminal and the inversion signal of the input signal are outputted from the latch means. A switch means 3 is provided between the output terminal of the latch means and the capacity means, and a resetting switch means 1 is provided for one terminal to which the capacity means is commonly connected. COPYRIGHT: (C)1996,JPO | ||||||
| 79 | Method and device for deciding humming distance between two multidimensional bit digital words | JP11095 | 1995-01-04 | JPH086807A | 1996-01-12 | SHIBARINGU ESU MAHANTO SHIETSU; BIBETSUKU JII PAAUOO |
| PURPOSE: To provide a method and a device for judging a humming distance with the minimum number of stages. CONSTITUTION: A current generator 14 for obtaining a non-matching bit position between two digital words 1 and 2 by means of exclusive OR operation, generating basic reference current against respective non-matching bits and adding them is provided. An added current signal is successively compared with a reference current signal being the multiple of a basic current signal and the reference current signal of a poststage is decided in accordance with a compared result. A digital signal showing the humming distance by converting the compared result of respective comparison stages 18, 20 and 22 is generated. | ||||||
| 80 | The signal processing device | JP33139188 | 1988-12-27 | JPH07114367B2 | 1995-12-06 | 久雄 加藤; 靖史 安達 |
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