| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | WAVEFORM A/D CONVERTER AND D/A CONVERTER | EP93913522.4 | 1993-06-15 | EP0601201B1 | 1999-09-22 | KAWABATA, Masayuki Emu Wai Hausu 202 gou |
| 182 | INTERFERENCE DEPENDENT ADAPTIVE PHASE CLOCK CONTROLLER | EP95939613 | 1995-10-27 | EP0744099A4 | 1999-09-01 | CONNELL LAWRENCE EDWIN; KANG DAVID DUKHO; HOLLENBECK NEAL WAYNE; ROECKNER WILLIAM J |
| An interference dependent adaptive phase clock controller method and system includes synthesis of a signal processing clock signal (307). An interference signal (311) dependent on a phase of the signal processing clock signal is measured, and a phase correction signal (317) is provided dependent thereon. A magnitude of the interference signal is reduced by adjusting the phase of the signal processing clock signal (307) dependent on the phase correction signal (317). | ||||||
| 183 | Low-distortion waveform generating method and waveform generator using the same | EP91105711.5 | 1991-04-10 | EP0451831B1 | 1999-07-07 | Furukawa, Yasuo |
| 184 | Integrated circuit with analog and digital portions and including thermal modeling | EP91311319.7 | 1991-12-04 | EP0495302B1 | 1999-03-03 | Elms, Robert Tracy; Schlotterer, John Carl; Engel, Joseph Charles; Murphy, William John |
| 185 | Complex number calculation circuit | EP96115064.6 | 1996-09-19 | EP0764915A3 | 1999-01-13 | Zhou Changming,; Shou Guoliang,; Yamamoto Makoto,; Takatori Sunao, |
A complex number calculation circuit for directly multiplying a complex number of an analog signal by a digital complex number as a multiplier. A capacitive coupling is used with a plurality of parallel capacitances corresponding to weights of bits of real and imaginary parts of the multiplier. Sign of the multiplier is represented by selection of outputs paths. A complex number calculation circuit for calculating approximated absolute value suitable for an analog architecture. Inverter circuits are used for linear inversion of analog values, and capacitive couplings are use for weighted addition. Analog maximum and minimum circuits with parallel MOSs are used for maximum and minimum calculation. |
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| 186 | Multiplication circuit | EP97101295 | 1997-01-28 | EP0786733A3 | 1998-12-02 | SHOU GUOLIANG; MOTOHASHI KAZUNORI; TAKATORI SUNAO; YAMAMOTO MAKOTO |
| Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X i corresponding to each clement of the first input data string is input to capacitance switching circuits 10 1 to 10 n through input terminals 1 1 to 1 n. m bit of digital control data A i corresponding to each element of the second input data string are input to each capacitance switching circuit 10 i, and each bit a j of the control signal A j is input to the corresponding multiplexer circuit 6 ij. In the multiplexer circuit 6 ij, the capacitances C ij corresponding to the value of each bit of the control signal a j are connected to the input terminal 1 i or the reference charge V STD. The voltages corresponding to the products of inputted analog voltages X i and the control signals A i are outputted from each capacitance switching circuit 10 i. The output voltages of each capacitance switching circuit 10 i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant. | ||||||
| 187 | Input/output interface circuit for digital and/or analog signals | EP93830436.7 | 1993-10-29 | EP0651503B1 | 1998-07-22 | Cordini, Paolo; Pedrazzini, Giorgio; Rossi, Domenico |
| 188 | Direct digital synthesizer | EP96303560 | 1996-05-20 | EP0749084A3 | 1998-06-03 | NAKAGAWA TADAO |
| A direct digital synthesizer capable of generating a desired frequency with small circuitry, low power consumption, and no spurious components. It includes an accumulator (1) for accumulating a frequency control word (K) for each pulse of a clock signal, a D/A converter (2) for converting the accumulation value of the accumulator to an analog voltage, an integrator (3) for smoothing the output of the D/A converter, a comparator for comparing the output of the integrator with a reference voltage (Vr), and for producing pulses at timings at which the output of the integrator reaches the reference voltage while the accumulation value of the accumulator is increasing, and a pulse generator (5) for producing pulses in synchronism with the rising edges of the output of the comparator. The output pulses of the pulse generator constitute an output of the direct digital synthesizer. | ||||||
| 189 | Apparatus having modular interpolation architecture | EP90310463.6 | 1990-09-25 | EP0426296B1 | 1998-04-22 | Asghar, Safdar M.; Bartkowiak, John G. |
| 190 | Improvements in systems for achieving enhanced frequency resolution | EP97111676.9 | 1992-05-28 | EP0810602A3 | 1998-04-08 | Johnson, Keith O.; Pflaumer, Michael W. |
A system for converting and encoding an analog signal to a digital format and subsequently decoding and converting said digital format to recover the analog signal, comprising means for monitoring the physical characteristics of an analog waveform to be converted to a digital format, means for frequency resolution enhancement to facilitate enhanced playback, means for converting said analog waveform to said digital format, means for encoding within said digital format control information indicative of the physical characteristics of said analog waveform, whereby said analog waveform can subsequently be more accurately reconstructed from said digital format, means for decoding from said digital format said control information indicative of certain specified physical characteristics of said analog waveform, means for converting said digital format signal to said analog waveform, and means for introducing compatible signal reconstruction compensation, in accordance with said control information during said converting process, said information facilitating subsequent more accurate reconstruction of said analog waveform from said digital format. |
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| 191 | Improvements in systems for archieving enhanced amplitude resolution | EP97111674.4 | 1992-05-28 | EP0810600A3 | 1998-04-08 | Johnson, Keith O.; Pflaumer, Michael W. |
A system for converting and encoding an analog signal to a standardized digital format and subsequently decoding and converting said digital format to recover the analog signal, comprising means for monitoring the physical characteristics of an analog waveform to be converted to a digital format, means for compatible amplitude resolution enhancement, means for converting said analog waveform to said digital format, means for encoding as compatible hidden code within said standardized digital format control information indicative of the physical characteristics of said analog waveform to facilitate said analog waveform being subsequently more accurately reconstructed from said digital format, means for decoding from said digital format said control information indicative of certain specified physical characteristics of said analog waveform, means for converting said digital format signal to said analog waveform, and means for introducing compatible signal reconstruction compensation, in accordance with said control information during said converting process, said information facilitating subsequent more accurate reconstruction of said analog waveform from said standardized digital format. |
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| 192 | One-chip semiconductor integrated circuit device | EP90115516.8 | 1990-08-13 | EP0413287B1 | 1997-12-10 | Fuse, Takeshi |
| 193 | Improvements in systems for achieving enhanced frequency resolution | EP97111676.9 | 1992-05-28 | EP0810602A2 | 1997-12-03 | Johnson, Keith O.; Pflaumer, Michael W. |
A system for converting and encoding an analog signal to a digital format and subsequently decoding and converting said digital format to recover the analog signal, comprising means for monitoring the physical characteristics of an analog waveform to be converted to a digital format, means for frequency resolution enhancement to facilitate enhanced playback, means for converting said analog waveform to said digital format, means for encoding within said digital format control information indicative of the physical characteristics of said analog waveform, whereby said analog waveform can subsequently be more accurately reconstructed from said digital format, means for decoding from said digital format said control information indicative of certain specified physical characteristics of said analog waveform, means for converting said digital format signal to said analog waveform, and means for introducing compatible signal reconstruction compensation, in accordance with said control information during said converting process, said information facilitating subsequent more accurate reconstruction of said analog waveform from said digital format. |
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| 194 | Improvements in hidden code side channels | EP97111675.1 | 1992-05-28 | EP0810601A2 | 1997-12-03 | Johnson, Keith O.; Pflaumer, Michael W. |
A method for converting and encoding analog signals to a standardized digital format, comprising the steps of monitoring the physical characteristics of an analog waveform to be converted to a standardized digital format, converting said analog waveform to said digital format, and encoding as compatible hidden code within said standardized digital format information indicative of said physical characteristics of said analog waveform, said information facilitating subsequent more accurate reconstruction of said analog waveform from said digital format. |
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| 195 | Improvements in systems for archieving enhanced amplitude resolution | EP97111674.4 | 1992-05-28 | EP0810600A2 | 1997-12-03 | Johnson, Keith O.; Pflaumer, Michael W. |
A system for converting and encoding an analog signal to a standardized digital format and subsequently decoding and converting said digital format to recover the analog signal, comprising means for monitoring the physical characteristics of an analog waveform to be converted to a digital format, means for compatible amplitude resolution enhancement, means for converting said analog waveform to said digital format, means for encoding as compatible hidden code within said standardized digital format control information indicative of the physical characteristics of said analog waveform to facilitate said analog waveform being subsequently more accurately reconstructed from said digital format, means for decoding from said digital format said control information indicative of certain specified physical characteristics of said analog waveform, means for converting said digital format signal to said analog waveform, and means for introducing compatible signal reconstruction compensation, in accordance with said control information during said converting process, said information facilitating subsequent more accurate reconstruction of said analog waveform from said standardized digital format. |
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| 196 | Improvements in signal encode/decode systems | EP97111671.0 | 1992-05-28 | EP0810599A2 | 1997-12-03 | Johnson, Keith O.; Pflaumer, Michael W. |
A method for converting and encoding an analog signal to a digital format and subsequently decoding and converting said digital format to recover the analog signal, comprising the steps of monitoring the physical characteristics of an analog waveform to be converted to a digital format, converting said analog waveform to said digital format, encoding within said digital formal control information indicative of the physical characteristics of said analog waveform, whereby said analog waveform can subsequently be more accurately reconstructed from said digital format, decoding from said digital format said control information indicative of certain specified physical characteristics of said analog waveform, converting said digital format signal to said analog waveform, and peak limiting and restoring, and introducing compatible signal reconstruction compensation, in accordance with said control information during said converting process, said information facilitating subsequent more accurate reconstruction of said analog waveform from said digital format. |
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| 197 | Sigma-delta digital-to-analog conversion system and process through reconstruction and resampling | EP97301232.1 | 1997-02-25 | EP0794621A2 | 1997-09-10 | Ma, Chingwo; Hsu, Wei-Chan; Yang, Inging |
A conversion system and method is disclosed for converting between digital and analog data signals. The conversion system comprises a signal input line for each digital data signal, a reconstructor-resampler unit for each digital data signal, a combiner, a modulator, a digital-to-analog converter, and a signal output line. Each signal line input couples to the respective reconstructor-resampler unit for the digital data signal. Each reconstructor-resampler unit then couples to a combiner which couples to a modulator. The modulator couples to the digital-to-analog converter that couples to the signal output line from which an analog output signal is produced. The reconstructor-resampler comprises a sampling member coupled to the signal line input and a polynomial interpolator member coupled to the sampling member and the modulator. Also, the modulator operates at a predetermined, or fixed, frequency regardless of the sampling frequency of the digital data signal. The steps of the conversion method include inputting a digital data signal having a sampling frequency, reconstructing and resampling the digital data signal to generate a resampled data signal, performing noise-shaping on the resampled data signal to generate a x-bit data signal from a modulator operating at a predetermined frequency regardless of the sampling frequency of any of the digital data signals, and converting the x-bit data signal to an analog data signal. In addition, an analog-to-digital conversion system and method is disclosed that comprises a signal line input, a decimator, a reconstructor-resampler a signal output line, and a modulator operating at a predetermined frequency to convert an analog data signal to a digital data signal. |
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| 198 | Multiplying apparatus | EP91311974.9 | 1991-12-23 | EP0494536B1 | 1997-09-10 | Tateno, Tetsuya, c/o Canon Kabushiki Kaisha |
| 199 | Semiconductor device, semiconductor circuit using the device, and correlation calculation device, signal converter, and signal processing system using the circuit | EP96101216.8 | 1996-01-29 | EP0725356A3 | 1997-07-23 | Kohchi, Tetsunobu; Miyawaki, Mamoru |
In a semiconductor device in which one terminal of each of capacitor (2) is connected to a corresponding multiple input terminal via a switch (3), and the other terminals of the capacitor are commonly connected to a sense amplifier (5), the other terminal of at least one capacitor is commonly connected to the sense amplifier (5) via a second switch (13), thereby reducing the circuit scale, increasing the operation speed, improving the operation precision, and saving the consumption power. |
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| 200 | Arithmetic processing apparatus and arithmetic processing circuit | EP96300597.0 | 1996-01-29 | EP0724225A3 | 1997-07-23 | Sakashita, Yukihiko; Ohzu, Hayao; Ouchi, Akihiro |
An arithmetic processing apparatus or circuit for performing charge redistribution by one or more capacitances connected to an input portion of each comparator are realized with improved arithmetic accuracy as suppressing dispersion and errors of gains of signals input into comparators, in such an arrangement that as the arithmetic processing apparatus is arranged to have a plurality of comparators, each having one or more capacitances connected to the input portion thereof, a sum of the capacitors connected to the input portions of each comparators 71 (or 72), C11 +•••+ C1n (or C81 +•••+ C8m), is substantially equalized among the plurality of comparators, or a ratio of the sum of the capacitors connected to the input portion of each comparator 71 (or 72), C11 +••• + C1n (or C81 +•••+ C8m), and input capacitance Cp1 (or Cp2) of the comparator is substantially equalized among the comparators. |
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