| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 41 | 센서 인터페이스를 가진 주파수 정보기반의 컴퓨터 | KR1020160177519 | 2016-12-23 | KR101838143B1 | 2018-03-15 | 이상철; 정우영 |
| 본발명은입력된원신호를주파수정보로계산하는하이브리드파동컴퓨터에있어서, 압전소자가마련된기판상에여러대역의주파수가내재된상기원신호가탄성파의형태로전달되어, 상기압전소자의발진을위치별로검출함에따라상기원신호의주파수를분리하는입력모듈; 상기입력모듈에서분리된상기원신호의주파수를입력받고, 주파수대역별로파동을증폭또는감쇠시키는진동증폭기또는진동감쇠기를각각하나이상구비하여, 입력받은상기원신호를주파수대역에서연산하는연산모듈; 및상기연산모듈에서이진화된주파수정보가디지털정보로저장하는저장모듈을포함하여, 상기원신호가파동의형태로인터페이스된다. 본발명에따르면, 표면탄성파의감쇠특성을이용하여아날로그의신호를입력모듈이주파수대역별로분리하고, 주파수대역의신호를입력값으로인터페이스에필요한연산이수행되어별도의퓨리에변환과정없이주파수대역에서정보를연산한다. 또한, 저장모듈에는주파수대역별 신호의정보가구분되어디지털로저장되기때문에, 인공신경망등의알고리즘과도연계가가능하다. | ||||||
| 42 | 견고한 난수 발생기 | KR1020017015656 | 2000-06-08 | KR1020020008849A | 2002-01-31 | 스프런크에릭제이 |
| 본발명에따라난수를발생하기위한방법및 장치(300)가발표된다. 제1 실시예에있어서, 난수를발생하는방법은제2 난수를생성하는것을포함한다. 의사난수는디지털난수발생기(304)로부터생성되고, 제1 난수는아날로그난수발생기(208-1)로부터생성된다. 제1 난수는의사난수와결합되어양 난수발생기출력의결과인제2 난수를생성한다. | ||||||
| 43 | 동시 아날로그-디지털 변환 및 승산 방법 | KR1020000014342 | 2000-03-21 | KR1020010006843A | 2001-01-26 | 데이비드샤오동양; 보이드에이파우러; 아바스엘가멜 |
| PURPOSE: A/D conversion and multiplication are simultaneously conducted by varying a RAMP signal and a BITX signal fed to a bit serial analog digital converter(ADC). CONSTITUTION: The multiplication by a coefficient X using a RAMP signal is attained by generating an M-RAMP signal with a voltage level different from a voltage level (40) of a 1-RAMP signal (24) not used for the multiplication by a coefficient 1/X. For example, to multiply a digital output of a bit serial ADC with a coefficient of 0.7, the 1-RAMP voltage level (40) is multiplied with 1.43 (that is, 1/0.7). The multiplied 0.7M-RAMP signal in excess of a maximum analog voltage (54) is rounded down. The change from the 1-RAMP voltage into the 0.7M-RAMP signal increases a voltage range (52) with respect to an analog input at which its digital output is equal to the unity. Thus, increasing the voltage level (40) attains the digital multiplication. | ||||||
| 44 | 인터리브형 디지털 피크 검출기 | KR1020000022440 | 2000-04-27 | KR1020000077098A | 2000-12-26 | 모저마이클에프. |
| 인터리브형디지털피크검출기는다중획득파이프를구비하고, 상기각 파이프는공용입력신호를수신한다. 각획득파이프는각 파이프에각 아날로그-디지털변환기의샘플시간을선택적으로지연시키기위해아날로그지연회로를통하여지연되는공용샘플클록신호를수신한다. 각파이프는아날로그-디지털변환기로부터디지타이징된출력을수신하고, 최대및 최소피크값을축적하는피크검출기를갖는다. 프로그램가능데시메이터(decimator)는샘플클록신호및 데시메이션값의함수로서샘플클록신호를데시메이팅하여획득클록을만들기위한데시메이션값을수신하여, 피크검출기로부터축적된최대및 최소값을저장하기위해래치회로를트리거(trigger)한다. 획득메모리는획득구간에걸쳐래치된최대및 최소피크검출기값을저장하고, 각획득파이프로부터의최대및 최소피크검출기값은획득파이프를위한획득구간에걸쳐최대및 최소피크검출기값을생성하기위한프로그램제어하에서획득구간에걸쳐비교가이루어진다. | ||||||
| 45 | 전송 데이타 정형 장치 | KR1019960057245 | 1996-11-26 | KR100228846B1 | 1999-11-01 | 니시자오아키히로; 다지리요시노리 |
| 전송 데이타를 정확히 재생할 수 있는 전송 데이타 정형 장치가 이하와 같이 제공된다. 전송 데이타 정형 장치는 전송 데이타 "a"를 기준 레벨 R과 비교해서 상기 전송 데이타 "a"가 상기 기준 레벨 R 이상인지 또는 이하인지에 따라, 2진 수치화된 데이타 "b"를 출력하는 비교 수단(1)과; 선정된 샘플링 클럭 "c"에 의해 데이타 "b"를 샘플화해서 데이타 "d"를 출력하는 샘플링 수단(2)과; 한 샘플링 클럭마다 선정된 수의 디지탈 데이타 "d"를 순차적으로 평균화해서 데이타 "e"를 출력하는 평균화 수단(3) 및; 데이타 "e"를 기준값 A 및 기준값 B와 비교해서, 데이타 "e"가 상기 기준값 A보다 더 크게 되기 때문에, 데이타 "e"가 상기 기준값 B보다 더 작게 될 때까지 한 논리값을 출력하고, 데이타 "e"가 상기 기준값 B보다 더 작게 되기 때문에, 데이타 "e"가 상기 기준값 A보다 더 크게될 때까지 다른 논리값을 또한 출력하는 또다른 비교 수단(4)으로 구성된다. | ||||||
| 46 | 반도체 장치, 이 장치를 갖는 반도체 회로, 상관연산장치,신호변환기,및신호처리시스템 | KR1019960002038 | 1996-01-30 | KR100191451B1 | 1999-06-15 | 오가와가쯔히사 |
| 캐패시터 수단의 한 단자들은 입력 신호의 정 또는 부 논리를 선택할 수 있는 제1스위치 수단을 거쳐 다입력 단자들에 접속되며, 캐패시터의 다른 단자들은 제2스위치를 거쳐 차동 입력/출력형 센스 증폭기의 제1차동 입력에 공통으로 접속된다. 캐패시터들의 공통 접속부는 차동 입력/출력형 센스 증폭기의 제2차동 입력에 접속되며, 제2차동 입력은 제1차동 입력의 극성에 반대되는 극성을 가져, 비트 수 증가에 기인한 회로 규모 증가를 억제하고 고속 산술 동작을 가능하게 한다. | ||||||
| 47 | 연산 처리 장치 및 회로 | KR1019960001897 | 1996-01-29 | KR100191449B1 | 1999-06-15 | 사까시따유끼히꼬; 오우찌아끼히로; 오즈하야오 |
| 입력부에 1개 이상의 캐패시턴스들이 접속되어 있는 다수의 비교기들을 갖도록 연산 처리 장치가 배열되어 있고, 각 비교기(71)(또는 72)의 입력부에 접속된 캐패시턴스들의 합, C 11 + ... + C 1n (또는 C 81 + ... + C 8m )은 다수의 비교기들에 대해서 실질적으로 동일하며, 각 비교기(71)(또는 72)의 입력부에 접속된 캐패시턴스들의 합, C 11 + ... + C 1n (또는 C 81 + ... + C 8m )과 비교기의 입력 캐패시턴스(C p1 )(또는 C p2 )과의 비가 다른 비교기들에 대해서도 실질적으로 동일하게 되어 있는 배치에 있어서, 각 비교기의 입력부에 접속된 1개 이상의 캐패시턴스들에 의한 전하 재분배를 수행하는 연산 처리 장치 또는 회로는 비교기에 입력된 신호들의 이득의 분산 및 오차를 억제하므로써 향상된 연산 정확도를 실현한다. | ||||||
| 48 | D/A 콘버터 | KR1019870700005 | 1986-05-09 | KR1019940002811B1 | 1994-04-02 | 아까기리겐죠 |
| 내용 없음. | ||||||
| 49 | 可调信号发生装置 | CN201020688734.0 | 2010-12-30 | CN202197260U | 2012-04-18 | 杨培; 白蓉蓉; 王建庭; 蒋耀丽; 陈殿玉; 齐燕; 王蕊; 李振; 陈世柱; 冯秀丽; 唐波; 刘忠志; 林海清; 向毅海 |
| 本实用新型涉及一种可调信号发生装置。所述装置包括：电压调控器，用于连续调节输出电压，并输出所述输出电压；模拟数字转换器，用于根据所述输出电压和参考电压，输出预定周期数的数字信号；计数器，用于计算所述预定周期数的数字信号中的目标电平的数量；数字信号发生器，用于根据所述目标电平的数量，生成目标信号。本实用新型可以在保持连续调节方式的前提下，提高生成的目标信号的精度。 | ||||||
| 50 | SIGMA-DELTA DIFFERENCE-OF-SQUARES LOG-RMS TO DC CONVERTER WITH FORWARD PATH MULTIPLIER AND CHOPPER STABILIZATION | PCT/US2011063972 | 2011-12-08 | WO2012078891A3 | 2013-01-10 | SILVA PAULO GUSTAVO RAYMUNDO; KOUWENHOVEN MICHAEL HENDRIKUS LAURENTIUS |
| A sigma-delta (S?) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a S? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order S? LOG- RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are S? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range. | ||||||
| 51 | SIGMA-DELTA DIFFERENCE-OF-SQUARES LOG-RMS TO DC CONVERTER WITH FORWARD AND FEEDBACK PATHS SIGNAL SQUARING | PCT/US2011063988 | 2011-12-08 | WO2012078899A3 | 2012-10-04 | SILVA PAULO GUSTAVO RAYMUNDO; KOUWENHOVEN MICHAEL HENDRIKUS LAURENTIUS |
| A sigma-delta (S?) difference-of-squares LOG-RMS to digital converter" by merging a traditional S? modulator with an analog LOG-RMS to DC converter based on a difference-of- squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path, High-order S? LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of S? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range. | ||||||
| 52 | SIGMA-DELTA DIFFERENCE-OF-SQUARES RMS-TO-DC CONVERTER WITH MULTIPLE FEEDBACK PATHS | PCT/US2011063980 | 2011-12-08 | WO2012078895A2 | 2012-06-14 | SILVA PAULO GUSTAVO RAYMUNDO |
| Architectures of S? difference-of-squares RMS-to-digital converters employing multiple feedback paths. Additional feedback paths enable a stable S? closed-loop behavior in different topologies where the RMS level of the quantization error processed by the squaring non-linearity is minimized. Such feedback paths include low pass filtered and constant gain feedback paths, low pass and high pass filtered paths or multiple low pass filtered paths. These can be combined with multiple integrators in the forward path, with frequency compensation provided by additional feed forward or feedback paths. Electronic configurability can further extend the total input referred dynamic range (DR) of such architectures. | ||||||
| 53 | RE-CONFIGURABLE MIXED-MODE INTEGRATED CIRCUIT ARCHITECTURE | PCT/US2004007958 | 2004-03-16 | WO2004084273A3 | 2005-03-24 | NAZARIAN HAGOP A |
| An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells. | ||||||
| 54 | CONFIGURABLE MIXED ANALOG AND DIGITAL MODE CONTROLLER SYSTEM | PCT/US0146750 | 2001-11-05 | WO0237298A2 | 2002-05-10 | DARMAWASKITA HARTONO; ELLISON RYAN SCOTT; YACH RANDY L; MORENO MIQUEL |
| A configurable mixed analog and digital mode controller may be fabricated as a single monolithic device such as an integrated circuit semiconductor die or a multi-chip package (MCP). The configurable mixed analog and digital mode controller may be a microcontroller and/or a digital signal processor (DSP) in combination with both analog and digital peripherals that may be configured and connected together, both before and during operation thereof, to function as a complete controller system. | ||||||
| 55 | DIGITAL WAVEFORM GENERATION USING TABLE LOOK-UP OF SIMULATED DELTA-SIGMA CONVERSION DATA | PCT/US9800924 | 1998-01-22 | WO9833137A3 | 1998-11-19 | RAGHAVAN GOPAL; JENSEN JOSEPH F |
| A digital waveform generator (10) reads out simulated ΔΣ ADC data (40) for a desired periodic analog waveform from a memory (38) and converts it, using a low-resolution high speed DAC (50), into a synthesized analog waveform (54). The ΔΣ digital waveform generator is preferably designed to take advantage of the natural evolution of device technologies. The memory is fabricated with older technologies, which tend to be slower but have a much higher integration. The DAC is implemented in more recent technologies, which are faster but have less integration. A speed up buffer (44) or buffers in intermediate speed intermediate integration technologies may be included to provide a bridge between the low speed memory and the low integration DAC. As the current technologies become more well developed, and thus more integrated, and new higher speed technologies take their place, the technologies for the various components will gradually change, but the architecture should remain viable and superior to the known digital generators. | ||||||
| 56 | MIXED-SIGNAL SYSTEM FOR PERFORMING TAYLOR SERIES FUNCTION APPROXIMATIONS | PCT/US2007087252 | 2007-12-12 | WO2008073975A3 | 2008-08-28 | REMY BRIAN; BRYANT MICHAEL D; FERNANDEZ BENITO R; YAN SHOULI |
| A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and calculates distance functions. The digital processor also includes a digital register for storing a magnitude scaling factor F (x 0, | ||||||
| 57 | SOLID-STATE SYNCHRO/RESOLVER CONVERTER | PCT/US2006007237 | 2006-02-28 | WO2006101687A3 | 2007-10-18 | KOSHR DANIAL L; TERPSTRA LARRY J |
| Methods and systems for simply and inexpensive converting the signals of solid-state sensors for use by analog systems and indicators. An embodiment of the system receives a DC voltage value from at least one sensor, converts the DC voltage value into one or more analog signals based on a reference AC voltage signal, and performs at least one of outputting or storing the generated analog signals. The conversion is performed digitally then converted to analog or is performed using an analog trigonometric converter. | ||||||
| 58 | LINEAR TRANSFORMATION CIRCUIT | PCT/US2006061655 | 2006-12-06 | WO2007076229A2 | 2007-07-05 | ABBASFAR ALIAZAM; AMIRKHANY AMIR; STOJANOVIC VLADIMIR; HOROWITZ MARK A |
| A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output. | ||||||
| 59 | APPARATUS, METHODS AND ARTICLES OF MANUFACTURE FOR DIGITAL MODIFICATION IN ELECTROMAGNETIC SIGNAL PROCESSING | PCT/US0331788 | 2003-10-07 | WO2004034307A3 | 2004-07-22 | AHMED WALID KHAIRY MOHAMED |
| Apparatus, methods and articles of manufacture are disclosed for digital signal modification. Various wave characteristics of an electromagnetic wave may be modified according to desired values. Those values are provided to one or more current sources, wherein the output values of the current sources are modified accordingly. | ||||||
| 60 | SWITCHED CAPACITOR SYSTEM, METHOD, AND USE | PCT/US0326198 | 2003-08-20 | WO2004021251A3 | 2004-06-17 | QUINN PATRICK J |
| An apparatus and method for adding input voltage signals. First 206 and second 208 input voltage signals are respectively sampled onto first 218 and second 228 capacitors during a first clock phase 202. In response to a second clock phase 204, the first sampled input voltage 206 that is held on the first capacitor 218 is coupled to the negative input terminal 236 of an amplifier 230, and the second sampled voltage 208 held on the second capacitor 228 is coupled to the positive terminal 240 of the amplifier 230. A feedback voltage is provided from the amplifier output 216 to the negative amplifier input 236 via the first capacitor 218 during the second clock phase 204. The first 206 and second 208 input voltage signals are added at the amplifier 230 during the second clock phase 204 to output 216 the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity. | ||||||
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