Signal processing circuit |
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| 申请号 | JP12843782 | 申请日 | 1982-07-23 | 公开(公告)号 | JPS5919428A | 公开(公告)日 | 1984-01-31 |
| 申请人 | Sony Corp; | 发明人 | SUZUKI TADAO; AKAGIRI KENZOU; NISHIGUCHI MASAYUKI; | ||||
| 摘要 | PURPOSE:To reduce noise modulation and to decrease the increase in noise and in distortion produced as the amplitude is compressed and expanded, by providing a frequency dependancy to an output of the 2nd D/A converting circuit and giving it to the 1st D/A converting circuit. CONSTITUTION:An input digital signal DX is given to the 1st D/A converting circuit 4 and also to the 1st converting circuit 7 functioning as an absolute value circuit. Further, a signal converted into an absolute value at the 1st converting circuit 7 is inputted to the 2nd D/A converting circuit, where the signal is converted into an analog signal, and the signal passes through the 2nd converting circuit 8 having frequency characteristics such as a high-frequency emphasis (low-frequency demphasis) circuit, is given to a multiplication terminal K of the 1st A/D converting circuit 4 so as to obtain the analog signal controlling the input digital information relating to the amplitude axis from the 1st D/A converting circuit. Thus, the noise modulation produced by the fact that the noise at a high frequency is subjected to the amplitude modulation with a low frequency component can be reduced. | ||||||
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| 说明书全文 | |||||||
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