Signal processing device

申请号 JP1487181 申请日 1981-02-03 公开(公告)号 JPS57130178A 公开(公告)日 1982-08-12
申请人 Nec Corp; 发明人 KANEDA HIROYUKI;
摘要 PURPOSE:To supplying a signal, which is detected as regular, as a timing signal to a processing circuit, by comparing an input signal and a reference signal with each other. CONSTITUTION:The input signal from a terminal 10 is converted to a digital value by an A/D converting part 20 and is supplied to a comparing circuit 30 and an adding circuit 50, and the circuit 30 generates a control signal 110 to the adding circuit 50, a storage circuit 60, and a counting circuit 70 when the input signal exceeds the reference signal from a reference level generating part 40, and the circuit 50 adds read contents of the circuit 60 and the input signal, and the circuit 60 stores the addition result. The circuit 70 counts the number of times of generation of the control signal on a basis of the command of the circuit 30 to obtain the number of times of addition, and this count value is supplied to a dividing circuit 80. The dividing circuit 80 divides the total after the last addition operation of the circuit 60 by the value of the circuit 70 to calculate an average value of the input signal and outputs it to a terminal 90.
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