Digital speech detection system
阅读：70发布：2021-06-18
专利汇可以提供Digital speech detection system专利检索，专利查询，专利分析的服务。并且A common time-shared speech detector that requires no per trunk detection circuitry is disclosed. The signal level on a trunk is applied to a common P.C.M. encoder in the time slot for the trunk and the resulting P.C.M. code is converted to digital threshold signals by a common digital threshold detector. Digital status and timing information for a plurality of speech lines are stored in circulating delay loops and processed in time sequence with common digital circuitry. Variable sensitivity is achieved by varying digital reference values for the lines which are also stored in circulating delay loops. Operate time, delay before hangover, and hangover are timed by multiplexed digital timing signals and varied in response to line activity signals to better accommodate talkers with different speech intensities. The output comprises time-slotted requests for connection or disconnection which can be used in a time assignment speech interpolation system.，下面是Digital speech detection system专利的具体信息内容。
1. In combination; a signal source; encoding means for periodically translating a signal from said source into pulse code; a threshold detector for translating said pulse code into a pattern of amplitude level signals; means for combining said patterns of amplitude level signals with data representing past amplitude level signal patterns generated by signals from said source and Timing signals which vary as a function of said data to assign a current connection requirement status code to said signal source; and means responsive to said connection requirement status code for controlling the transmission of signals at said signal source.
2. A common control signal level detecting system comprising; a plurality of signal sources; time divided scanning means for scanning said signal sources; common time-shared means for translating the amplitude of the signal present at each signal source into a code during the time slot for said signal; common time-shared means for translating said code into a selected amplitude level signal pattern; common time-shared comparison means for comparing said amplitude level signal pattern with data representing previous amplitude level signal patterns for the same signal source; means responsive to said data for controlling the sensitivity of said comparison means during the comparison; and means responsive to said comparison means for generating control signals for each of said signal sources.
3. The common control signal level detecting system of claim 2 further comprising; means selectively responsive to said comparison for altering said data representing previous amplitude level signal patterns.
4. The common control signal level detecting system of claim 3, further comprising; common time-shared timing means responsive to said data for generating selected timing signals in the time slot of said signal source; and means for connecting said selected timing signals as inputs to said comparison means.
5. In combination; a plurality of signal sources; means for repetitively sampling the amplitude level present at each of said signal sources; a common encoder for translating sampled signal amplitudes at each source into a pulse code; a common threshold detector for translating said pulse code into a selected pattern of discrete amplitude level signals; common combination means for combining the pattern of discrete amplitude level signals for a source with data representing preceding patterns of discrete amplitude level signals for said source to determine the current connection requirement status of said source; means responsive to said data for controlling the sensitivity of said combination means to said amplitude level signals for said source; and means responsive to said current connection requirement status for controlling the transmission of signals at said source.
6. The combination of claim 5 wherein said combination means further comprises; means for converting a selected portion of said pattern of amplitude level signals into a line activity signal for said signal source; a source of timing signals; and a plurality of state detectors, each being responsive to a selected combination of said line activity signal, said timing signals, and said data representing preceding patterns of amplitude signals for said source.
7. The combination of claim 6 further comprising; means responsive to the output signals of said plurality of state detectors for altering said data representing preceding patterns of amplitude level signals in accordance with a predetermined speech detector sensitivity statistical distribution.
8. In combination; a plurality of analogue signals; an encoder for translating each of said analogue signals into a code when said signal is applied to said encoder; a threshold detector for translating said code into discrete amplitude level signals; a common time-divided memory, synchronized with the application of said signals to said encoder, containing data representing previous amplitude level signals generated by each of said signals; combination means for combining the amplitude level signals generated by the application of each analogue signal with the data associated with that signal in said time-divided memory and timing signals which vary as a funcTion of said data representing previous amplitude level signals to generate a control signal; and means responsive to said control signal for controlling the connection of said signal sources to transmission channels.
9. The combination of claim 8 wherein said data representing previous amplitude level signals generated by each of said signals comprises; a first code associated with each of said signals for controlling the sensitivity of said combination means for said code''s associated signal when said associated signal is next applied to said encoder; and a second code associated with each of said signals for indicating the connection requirement status of its associated signal at the time of said associated signals last application to said encoder.
10. A signal controlled signal level detecting system comprising; a time-shared encoder for converting an input signal into a pulse code signal; means for repetitively applying the signal on each of a plurality of lines to said encoder in a selected time slot; a time-shared threshold detector for converting the code signal output of said encoder into a plurality of discrete amplitude level signals; variable sensitivity means for combining selected ones of amplitude level signals generated by the application of the signal on a line with data representing the current sensitivity of said level detecting system to signals on said line and the current connection requirement status of said line, in the time slot for said line, to generate a line activity signal for said line; and means responsive to said line activity signal for generating an updated connection requirement status code that controls connection of said line to a transmission channel.
11. The system of claim 10 wherein said variable sensitivity means further comprises; a time-divided store synchronized with the occurrence of time slots of said lines; a plurality of sensitivity codes in said store, each associated with one of said lines, for controlling the sensitivity of said level detecting system to the signals on their respective lines; and means responsive to selected combinations of said sensitivity codes and said amplitude level signals for generating said line activity signal.
12. The system of claim 11 wherein said variable sensitivity means further comprises; sensitivity update means responsive to the current connection requirement status code for a given line and the sensitivity code associated with said given line in said store for altering said sensitivity code.
13. The system of claim 12 wherein said sensitivity update means is further responsive to selected timing signals occurring in the time slot of said given line.
14. A common control signal level detecting system comprising; a time-shared encoder for translating an input into a selected code; means for repetitively applying the signals on each of a plurality of lines to said encoder in a selected time slot; a time-shared threshold detector for translating the code output of said encoder into a plurality of discrete amplitude level signals; a timing means, containing a plurality of timing codes, for periodically altering each of said timing codes, where each of said timing codes is assigned to a selected one of said lines; time-shared state detection means responsive to the amplitude level signals occurring in the time slot for a given line and the occurrence of a selected timing code assigned to said given line for generating a selected connection requirement status code for said given line; and time-shared means for altering the timing code assigned to said given line at a rate determined by said connection requirement status code.
15. The signal level detecting system of claim 14 wherein said timing means further comprises; a recirculating time-divided store for storing said plurality of timing codes; and timing code detector means responsive to the applicatIon of said timing codes in said store for generating selected timing signals.
16. The signal level detecting system of claim 14 wherein said means for altering timing codes further comprises; generator means for generating enable pulses occurring in synchronism with selected ones of said time slots; arithmetic circuitry for altering the timing code associated with a given line, in the time slot for said line, in response to the application of an enable pulse to said arithmetic circuitry in said time slot.
17. The signal level detecting system of claim 16 wherein said generator means simultaneously generates a plurality of enable pulse trains having different pulse recurrent frequencies; and said arithmetic circuitry is responsive to the pulses in a selected one of said plurality of pulse trains.
18. The signal level detecting system of claim 17 further comprising; means responsive to said connection requirement status code of said given line for selecting the pulse train to be applied to said arithmetic circuitry.
19. In a time-divided signal processing system; an encoder for translating a signal on a line applied in a selected time slot into a pulse code; a threshold detector for translating said code into a pattern of discrete amplitude level signals; a first-time divided memory; a second time-divided memory; sensitivity circuitry for combining a selected portion of said pattern of signals with data in a first time-divided memory location associated with said time slot to generate an activity signal for said line; state detection circuitry for combining said activity signal with data in a second time-divided memory location associated with said time slot to generate a selected connection requirement status code for said line; and means responsive to said selected connection requirement status code for controlling the connection of said line to a transmission channel.
20. The system of claim 19 wherein said sensitivity circuitry further comprises; a plurality of comparators for generating selected signals when enabled; means connecting the output of said first time-divided memory as an input for each of said comparators; and means for connecting selected ones of said amplitude level signals as inputs to selected ones of said comparators.
21. The system of claim 19 wherein said state detection circuitry further comprises; a plurality of state detectors for generating selected signals when enabled; means connecting the output of said second time-divided memory as an input to each of said state detectors; means connecting said line activity signal as an input to selected ones of said state detectors; and means for connecting the logical complement of said line activity signal as an input to selected others of said state detectors.
22. The system of claim 21 further comprising; means responsive to said selected signals generated by said plurality of state detectors for altering said data in said second time-divided memory location.
23. The system of claim 22 wherein the means for altering said data alters said data in accordance with a line activity statistical distribution.
24. The system of claim 20 further comprising; write means for altering said data in said first time-divided memory location; means connecting the current connection requirement status code as an input to said write means; and means connecting the output of said first time-divided store as an input to said write means.
25. In a time-divided signal level detecting system; a plurality of input lines carrying analogue signals; a P.C.M. encoder for converting the analogue signal on each line into a pulse code in the time slot for the line; a threshold detector for converting said pulse code for said line into a pattern of discrete amplitude level signals in said time slot; means responsive to a first portion of said pattern, selected data stored in a First time-divided memory representing past portions of said pattern applied in said time slot, and selected timing codes, for generating a line activity signal; and means responsive to said line activity signal, a second portion of said pattern, and a status code stored in a second time-divided memory representing the past connection requirement of said line for generating a selected status code representing said lines current connection requirement.
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