| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 201 | Method and apparatus for DC-level constrained coding | US10695531 | 2003-10-28 | US06917314B1 | 2005-07-12 | Mats Oberg |
| A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word. | ||||||
| 202 | Data conversion system | US10452166 | 2003-05-30 | US20040108943A1 | 2004-06-10 | Kazuyuki Aoyama |
| A worker defines a first conversion rule to convert data in a data format of a cooperative operation objective system as an input into data in a data format of first common data, a second conversion rule to convert data in the format of the first common data into data in a data format of a second common data, and a third conversion rule to convert data in the data format of the second common data into data in a data format of a cooperative operation objective system as an output. According to the rules, conversion processing is executed to convert data in the data format of the input system into data in the data format of the output system. | ||||||
| 203 | Device for receiving digital signals | US10416009 | 2003-09-30 | US20040056680A1 | 2004-03-25 | Stephane Boirin; Jean-Yves Couleaud |
| The invention relates to a device for receiving digital signals on the basis of two different standards conveyed on the same medium (2, 3, 4), comprising: logic-level conversion means (1) receiving the digital signals and converting their logic levels into logic levels on the basis of a single standard, means (7) for receiving signals coded on the basis of a first standard, which signals are output by the logic-level conversion means (1), means (10) for converting signals coded on the basis of a second standard into signals coded on the basis of the first standard, which signals are output by the logic-level conversion means (1), means (9) for transferring signals output by the means (10) for converting signals coded on the basis of a second standard into signals coded on the basis of the first standard to the reception means (7) upon reception of signals coded on the basis of the second standard, or for transferring signals output by the logic-level conversion means (11) upon reception of signals coded on the basis of the first standard. | ||||||
| 204 | Binary encoding circuit | US10325707 | 2002-12-20 | US20030122693A1 | 2003-07-03 | Luigi Pascucci |
| A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example. | ||||||
| 205 | Multi-function type absolute converter | US09977393 | 2001-10-16 | US06469651B1 | 2002-10-22 | Yoshinori Ito |
| A multi-function type absolute converter comprises a sensor I/O port having a plurality of sensor connection terminals that can be connected to a plurality of absolute sensors, a conversion circuit for converting absolute sensor detection signals input via the sensor connection terminals to digital position signals, a PLD that can perform prescribed processing on the digital position signals thus generated, a host I/O port having output terminals for outputting the digital position signals and signals generated by the programmable logic device, a switching circuit for switching sensor connection terminals, and a control circuit for controlling each part, the control circuit comprising mainly a CPU, ROM and RAM. The inclusion of a PLD enables the multi-function type absolute converter to be flexibly adapted to user specification. | ||||||
| 206 | Code converter for coding and decoding digital data | US09984478 | 2001-10-30 | US20020097173A1 | 2002-07-25 | Satoshi Itoi |
| A code converter of the present invention converts m data bits to n channel bits (m | ||||||
| 207 | Demodulating device, demodulating method and supply medium with predetermined error length | US09378064 | 1999-08-20 | US06340938B1 | 2002-01-22 | Toshiyuki Nakagawa |
| A demodulating device of the present invention in which an error code/constraint length determining unit, a minimum run continuation restricting code detecting unit and a minimum run/maximum run compensating code detecting unit specify a constraint length of a code having a predetermined length including an error and inverse conversion units and an error data demodulation table demodulate the code based on the specified constraint length, thus reducing error propagation by a simpler constitution when bit shift error is caused. | ||||||
| 208 | Method and apparatus for compressively coding/decoding digital data to reduce the use of band-width or storage space | US09369204 | 1999-08-06 | US06310564B1 | 2001-10-30 | Masakazu Fujimoto |
| There are provided coding and decoding apparatuses and coding and decoding methods in which digital data are represented by bits fewer than those by which digital data according to the prior art apparatuses and methods are represented, and original data can be decoded correctly without degrading its precision. The number of continuous zeros from the LSB of the digital data 103 is counted. The number on continuous zeros plus one is subtracted from the number of bits of the digital data 103, resulting in a number of bits to-be-allocated 105, according to which, bits are allocated starting from the most significant bit (MSB). The number of omitted bits is calculated according to the number 105 (114), and lower bits represented as the MSB “1” and bits “0”. The lower bits 116 are coupled to a lower side of a code 115 to restore original digital data 151. | ||||||
| 209 | Logic circuit and signal transmission method | US09267596 | 1999-03-15 | US06259383B1 | 2001-07-10 | Yoshio Miki |
| In the transmission of a logic signal, there is a reduced maximum value and a reduced average value of the number of bits varied by transforming an input level representation original logic signal having n bits into a transition representation logic signal of m groups with only a maximum of k bits varied, wherein k and m are integer numbers, n is greater than k and each value of k and m is greater than 1. The transformed logic signal of m groups is transmitted. The transmitted logic signal of m groups is then transformed into the original logic signal having n bits. A maximum number of bits varied is k, which can be below n/2 as a maximum, which is less than an average bit variation of the input original signal. | ||||||
| 210 | Partitioned DC balanced (0,6) 16B/18B transmission code with error correction | US09346230 | 1999-07-01 | US06198413B1 | 2001-03-06 | Albert X. Widmer |
| A coding system includes methods and apparatus for producing a (0,6) run length limited rate 16B/18B code. The code produced is dc balanced and capable of operating near the theoretical performance limits for a 16B/18B code. This means the code is near optimum for run length and digital sum variation for a 16B/18B code. In one aspect of the invention, each 16-bit input data stream or block is broken into a 9-bit and a 7-bit sub-block and encoded separately while maintaining both dc balance and run length constraints across all block and sub-block boundaries. The present invention also provides a plurality of special purpose control characters such as commas, delimiters, idle characters, etc., by using the extra bits in the coded blocks whereby the special characters may be readily distinguished from data, while at the same time maintaining the dc balance and run length limitations in such characters. The 16B/18B transmission coding system of the invention also provides error correction techniques. | ||||||
| 211 | Circuit and method of converting a floating point number to a programmable fixed point number | US499988 | 1995-07-10 | US6144977A | 2000-11-07 | Philip B. Giangarra; James D. Dworkin |
| A programmable numeric converter (10) converts a floating point number to a fixed point format by selecting the proper offset. The mantissa is loaded with an implied value one into the least significant, or most significant, bits of the shifter (20). The programmable offset is added (24) to the exponent to determine the number of shifts to the mantissa bits. The number of bits of resolution necessary in the fixed point number is reduced because the offset can be programmed to move the decimal point to the left, or to the right, to provide accuracy wherever the significant digits are located. That is, the decimal point is moved left to provide more resolution in the fractional portion of the fixed point number for small numbers. Alternately, the decimal point is moved right to provide more resolution in the whole number portion of the fixed point number for large numbers. | ||||||
| 212 | Recognizer/converter for arabic and other language codes | US157296 | 1980-06-06 | US4415766A | 1983-11-15 | Syed S. Hyder |
| The invention relates to a code converter with the specific capability of converting certain predetermined combinations of two or more code words of a first coding system to a single code word of a second coding system. The invention also relates to a converter with means for recognizing the combination, and to the recognizer per se. In a specific application, the converter system is for converting code words of a presently existing coding system, which are representative of characters in the Arabic-Farsi languages, and all languages written in Arabic scripts, to code words of a second coding system. The Arabic-Farsi languages include special characters, which comprise an overdot and an undercharacter, and each of these special characters is represented by two code words. The converter compresses the two code words to a single respective code word. The converter includes a recognizer to recognize the code words for the special characters, and a converting circuit for converting the two code words representative of respective ones of the special characters to a single respective code word. | ||||||
| 213 | Recognition of a received signal as being from a particular transmitter | US890464 | 1978-03-27 | US4178549A | 1979-12-11 | Gregory W. Ledenbach; Dennis E. Morris |
| A system for recognizing a received encoded signal as being from a particular transmitter is disclosed. An encoder encodes a signal to have a predetermined sequence of pulses of three different predetermined sequence of pulses of three different predetermined durations within a constant bit interval in accordance with a trinary code; wherein each of the different predetermined durations corresponds to a different bit. A decoder is coupled to the receiver for recognizing the received encoded signal as being from the particular transmitter includes a programmable digital logic signal generator that is programmed in accordance with the trinary code for generating a programmed digital logic signal having a predetermined sequence of different digital words corresponding to the predetermined sequence of pulses of different predetermined durations in the transmitted encoded signal; a code converter for converting the received encoded signal to a decoded digital logic signal having digital words in accordance with the selected code by measuring and comparing the relative durations of the pulse and the non-pulse time during each bit interval; a comparator for comparing the decoded digital logic signal with the programmed digital logic signal; and a control logic circuit coupled to the programmable signal generator, the code converter and the comparator for synchronizing the programmed digital logic signal with the decoded digital logic signal and for recognizing the received encoded signal as being from the transmitter when said comparison indicates a predetermined number and sequence of valid comparisons between the decoded digital logic signal and the programmed digital logic signal. | ||||||
| 214 | System for the transmission and reception of encoded information | US703278 | 1976-07-07 | US4162487A | 1979-07-24 | Malcolm Macaulay |
| A system for the transmission and reception of complex codes which provides a simple means for selection by an operator of the item to be encoded and transmitted. The invention allows the transmitted signal to be decoded and to be shown visually without requiring any assistance from an operator. Standard electrical and electronic components are used in the equipment of the invention. This invention is especially useful for signalling messages in Chinese or Japanese text, which both have a large number of characters and present difficulties in transmission and reception with conventional teleprinter machines. | ||||||
| 215 | Non-return to zero mark to non-return to zero level code converter | US736812 | 1976-10-29 | US4063235A | 1977-12-13 | Volker Ludwig |
| A circuit arrangement for reshaping a pulse edge data signal whose pulse edges signal binary values of data into an amplitude data signal whose amplitudes signal the binary values of the data includes a pulse generator to produce a timing signal having a period duration which is equal to the duration of the individual binary values. A pulse shaper is fed with the pulse edge data signal and emits a rectangular signal whose rectangular pulses are of short duration and coincide with the pulse edges of the pulse edge data signal. A first bistable trigger stage and a second bistable trigger stage are provided, each of which has a setting input, a data input, a pulse train input and an output, the output emitting signals having binary values which signal the stable states of the two trigger stages. The setting input of the first trigger stage is supplied with the rectangular signal and the pulse train input of the first trigger stage is fed with a timing signal. The first trigger stage assumes one of its two stable states when a rectangular pulse of the rectangular signal occurs and assumes the other of its two stable states when, in the absence of the rectangular pulses, a pulse edge of the timing signal is present at the pulse train input of the first trigger stage. The output of the first trigger stage is connected to the data input of the second trigger stage and the timing signal is fed to the pulse train input of the second trigger stage. The second trigger stage assumes the states of the first trigger stage when one of the edges of the timing signal occurs, and the amplitude data signal is emitted by way of the output of the second trigger stage. | ||||||
| 216 | Prevention of non-allowed character combinations | US552773 | 1975-02-24 | US3976972A | 1976-08-24 | Kurt Arvid Aman |
| A method is disclosed to prevent the transmission of non-allowed character combinations of signal elements which have for example, a route administrating or a control function. In the sender a sequence of the information carrying signal elements is formed. The sequence is divided into parts each including N-n signal elements. New character signals are formed by completing each of such parts with n signal elements, selected in such manner that only characters which are allowed are formed and the formed characters are transmitted to the receiver. In the receiver such parts including N-n signal elements are restored by removing the n signal elements for each character signal. Then a sequence of the original information carrying signal elements is formed and the last mentioned sequence of signal elements is divided in the original character signals consisting of N information elements. | ||||||
| 217 | Telecommunications system for the hearing impaired utilizing baudot-ascii code selection | US39955373 | 1973-09-21 | US3896267A | 1975-07-22 | SACHS REYNOLD; CICCHIELLO FRANK |
| A data terminal has a keyboard capable of encoding data. A switch determines whether a diode matrix will encode keyboard entries in Baudot or ASCII code. A modem couples the encoded keyboard data to telephone lines for transmission to another terminal station. Data may be received by the terminal in either Baudot or ASCII code. The received data is translated to alphanumeric video signals that may be displayed on a conventional television receiver.
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| 218 | Tree counter code simulator | US42085673 | 1973-12-03 | US3895185A | 1975-07-15 | RAMSEY ROBERT W |
| Use of a tree counter for translating, storing and displaying Morse or similar code signals.
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| 219 | Apparatus for converting teletypewriter signals for use in digital logic circuits | US32024073 | 1973-01-02 | US3818134A | 1974-06-18 | FIRMAN C |
| Teletypewriter signals including a start signal, data information defined by signal transitions occurring within a predetermined number of repetitive uniform data periods, and a stop signal are operated upon so that they are converted to signals adapted for use in digital logic circuits in a unique manner which avoids electromagnetic interference of both the radiated and conducted types. The start signal is used for producing a delayed enabling signal after the occurrence of the signal transition point of the first of the uniform data periods and a clock, responsive to the enabling signal, produces sampling pulses at the same rate as the repetition rate of the uniform data periods. The sampling pulses sample the incoming data information within each data period and produce commensurate output data information in the form of pulses usually of low voltage type for use in digital logic circuits. A counter responsive to the same enabling circuit sequentially counts the number of sampling pulses and produces an output signal indicative of a cummulative count equal to the predetermined number of repetitive uniform data periods and the output signal is employed to reset both the clock and the counter means. As a result, all the signals adapted for use in digital logic circuits are produced and generated at times other than during the occurence of signal transitions of the incoming teletypewriter signal thus eliminating the generation of false signals as well as the effects of unwanted electromagnetic interference of both the radiated and conducted types.
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| 220 | Synchronous line control discriminator | US3754217D | 1971-12-20 | US3754217A | 1973-08-21 | BELL N; COOPER R; NAGLE F; NEWLIN F; STADLER W |
| The described apparatus is interposed between the modem or line adapter of a synchronous transmission line and the data processor and will identify for the processor, the code in which data is being received. The discriminator is particularly useful in a system where any one of a number of data terminals using different transmission codes can be connected to one of the ports of the processor. In use, the discriminator examines, at each bit time, the last grouping of bits it has received to detect the presence of a code identifying character. When it detects one such character, the system waits until another character is received to determine if the second character is consistent with the tentatively identified code. If not, the system resets to continue looking for a new identification character. The system continues hunting until a transmission code is fully identified. The discriminator then notifies the processor of the code in which the data is being received.
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