A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes. By evaluating many error-correcting codes according to the method, an optimal code according to selected criteria can be obtained.

An I/O port (9) enables to intercept the SCSI communications between a SCSI control circuit (7) and host system regardless at the data transmission mode or at data reception mode. When the SCSI communications are intercepted, a system controller (11) transfers data from a main memory (12) to a buffer memory (5) through the SCSI control circuit (7) at the data transmission mode of the SCSI control circuit (7) and performs the self-diagnosis of the SCSI control circuit (7) by comparing data transmitted to the buffer memory (5) with the test data stored in the main memory (12). At the data reception mode of the SCSI control circuit (7), the system controller (11) stores data read from the main memory (12) to the buffer memory (5) through the buffer memory control circuit (6) and performs the self-diagnosis of the SCSI control circuit (7) by comparing data read from the I/O port (9) with data stored in the main memory (12). Thus, it is possible to vest the self-diagnosis function to the disk control system comprising the SCSI control circuit as the communicating means with the host system so that to improve its liability.

A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones.

In one embodiment, the circuit comprises for generating a parity bit, P_k, for each of K data fields in the ECC word; for comparing logical combinations of these parity bits to logical combinations of the memory check bits, C_j, to form H bits; and for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non carry) sum of the syndrome bits to detect syndrome generation path failures. This D bit may also be used to determine if the data bits in an ECC word are correct, a number of cycles before the completion of the normal ECC operation.