| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | Integrated viterbi decoder and method for testing the same | EP86115031.6 | 1986-10-29 | EP0221507A3 | 1989-01-18 | Shimoda, Kaneyasu; Yamashita, Atsushi; Katoh, Tadayoshi |
An integrated viterbi decoder structure and method, in which the viterbi decoder receives test input signals at a distributor (l), an ACS circuit (2) and a path memory (3) and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder. |
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| 62 | Integrated viterbi decoder and method for testing the same | EP86115031.6 | 1986-10-29 | EP0221507A2 | 1987-05-13 | Shimoda, Kaneyasu; Yamashita, Atsushi; Katoh, Tadayoshi |
An integrated viterbi decoder structure and method, in which the viterbi decoder receives test input signals at a distributor (l), an ACS circuit (2) and a path memory (3) and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder. |
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| 63 | PROCESSING DATA TO IMPROVE A QUALITY OF THE DATA | US15674235 | 2017-08-10 | US20180373579A1 | 2018-12-27 | Vijay Singh RATHORE; Suneet KUMAR GARG; Manisha SURI SRIRAMAN; Alok JOHRI; Manoj KRISHNA; Vasuprad KANADE; Ayan CHAKRABORTY; Harsh H. SHARMA; Shrikant SARDA |
| A first device may receive data from a set of second devices to be processed to determine a quality of the data. The data may include first data stored by the set of second devices, second data provided toward a third device, or third data related to fourth data. The first device may process the data using a first set of techniques to prepare the data for processing. The first device may process the data using a second set of techniques to improve the quality of the data and to form processed data. The first device may provide the processed data toward the set of second devices to replace the data stored by the set of second devices to permit the set of second devices to use the processed data. The first device may perform an action after providing the processed data toward the set of second devices. | ||||||
| 64 | VOICE QUALITY MONITORING SYSTEM | US15571198 | 2016-05-05 | US20180287918A1 | 2018-10-04 | Doh-Suk KIM |
| This disclosure falls into the field of voice communication systems, more specifically it is related to the field of voice quality estimation in a packet based voice communication system. In particular the disclosure provides methods, computer program products and devices for reducing a prediction error of the voice quality estimation by considering forward error correction of lost voice packets. | ||||||
| 65 | System and method of belief propagation decoding | US14941789 | 2015-11-16 | US09806743B2 | 2017-10-31 | Toshiaki Koike-Akino; David Millar |
| A method for decoding a codeword transmitted over a channel demodulates data received over the channel to produce an initial estimate of belief messages for bits of the codeword and decodes the codeword using a belief propagation (BP) decoding that iteratively passes the belief messages between a set of variable nodes representing the bits of the codeword and a set of check nodes representing parity-check constraints on the bits of the codeword until a termination condition is met. The BP decoding selects a look-up table based on a probability of the belief messages and maps, using the look-up table, values of at least two incoming belief messages to values of at least one outgoing belief message that forms an incoming belief message in a subsequent iteration of the BP decoding. | ||||||
| 66 | SYSTEM AND METHOD FOR TRANSFORMING AND COMPRESSING GENOMICS DATA | US15155902 | 2016-05-16 | US20160357812A1 | 2016-12-08 | Daniel Greenfield; Alban Rrustemi |
| This invention relates to the quality scores of bases produced from high throughput genomic sequencing, in particular to transforming the quality scores for improved compressibility. A method for transforming these quality scores is described whereby a quality score is modified by utilising a Bayesian model based on Coding Theory combined with search results from a genomic corpus. A related method is described for efficient searching for a Read in a genomic corpus so as to find all matching symbols up to a given Hamming-distance or Edit-distance. | ||||||
| 67 | MANUFACTURING TESTING FOR LDPC CODES | US14334532 | 2014-07-17 | US20150019926A1 | 2015-01-15 | Yu Kou; Lingqi Zeng |
| An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding. | ||||||
| 68 | Multi-stage forward error correction decoding | US13427792 | 2012-03-22 | US08429482B1 | 2013-04-23 | Robert E. Payne; Graham Johnston |
| In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to one or more of the decoder stages and is configured to generate, for each of one or more of the plurality of decoder stages, a respective compressed error mask from the error mask produced by the decoder stage. A buffer circuit is coupled to the compression circuit and is configured to buffer the compressed error masks. A decompression circuit is coupled to the buffer circuit and is configured to decompress each of the compressed error masks. A combination circuit is coupled to the decompression circuit and is configured to combine the decompressed error masks into a single error mask. | ||||||
| 69 | Manufacturing testing for LDPC codes | US12387720 | 2009-05-05 | US08266497B1 | 2012-09-11 | Yu Kou; Lingqi Zeng |
| A technique for tested is disclosed herein. A low-density parity-check (LDPC) code is received. For the received LDPC code, an error rate function is generated that is a function of a number of iterations. A number of test iterations and a passing error rate are determined using the error rate function. One or more storage media are tested using the LDPC code, the number of test iterations, and the passing error rate. | ||||||
| 70 | METHOD FOR CONSTRUCTING A HISTOGRAM | US12912688 | 2010-10-26 | US20120102377A1 | 2012-04-26 | Krishnamurthy Viswanathan; Ram Swaminathan |
| A method for constructing a histogram can include sampling attributes in a column of a database on a server and determining a bucket set for the histogram based on a number of buckets that represents a distribution of the attributes with minimum error. A bucket in the bucket set includes boundaries and an approximation of a count of attributes falling within the boundaries. The method further includes determining a precision for encoding the approximation, such that the histogram having the bucket set fits within a storage limit on a tangible computer-readable medium. The histogram can then be stored for the database on a tangible computer-readable medium by encoding the approximation with the precision. | ||||||
| 71 | DTV transmitting system and receiving system and method of processing television signal | US13078854 | 2011-04-01 | US08145979B2 | 2012-03-27 | Won Gyu Song; In Hwan Choi; Kook Yeon Kwak; Byoung Gill Kim; Jin Woo Kim; Hyoung Gon Lee; Jong Moon Kim |
| A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction (FEC) and expanding the FEC-coded enhanced data. The packet generator generates first and second enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. The first enhanced data packet includes an adaptation field including the pre-processed enhanced data and second enhanced data packet includes a payload region including the pre-processed enhanced data. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction (FEC), and the trellis encoder performs trellis encoding on the RS-coded data packets. | ||||||
| 72 | Spherical lattice codes for lattice and lattice-reduction-aided decoders | US11694241 | 2007-03-30 | US08091006B2 | 2012-01-03 | Narayan Prasad; Xiaodong Wang; Mohammad Madihian |
| Methods and apparatus for designing spherical lattice codebooks for use in data transmission systems are provided. A spherical lattice codebook is constructed by determining the channel statistics of one or more channels, which can be accomplished by observing a sufficiently large set of channel realizations. After determining the channel statistics, an expression for the error probability of the decoder or expressions for bounds on the error probability and expressions for the corresponding gradients are determined. The gradient is then used in an optimization technique to produce a spherical lattice codebook which is subsequently used for transmission. | ||||||
| 73 | System and method for characterizing error correction performance for digital data transport over an IP network | US11337367 | 2006-01-23 | US07788568B1 | 2010-08-31 | Renxiang Huang; Claudio Lima; Jim Black |
| A method for characterizing performance of an error correction scheme for digital data transport is provided. A digital data packet stream within an Internet Protocol packet stream is monitored for a first set of packet errors. Errors of the Internet Protocol packet stream are corrected according to the error correction scheme to produce a corrected Internet Protocol packet stream. The digital data packet stream within the corrected Internet Protocol packet stream is monitored for a second set of packet errors. The first and second sets of packet errors are compared to characterize the performance of the error correction scheme. | ||||||
| 74 | BIT ERROR PROBABILITY ESTIMATION METHOD AND RECEIVER EMPLYING THE SAME | US11565760 | 2006-12-01 | US20080134006A1 | 2008-06-05 | Yuan Xia |
| A bit error probability (BEP) estimation method includes de-shaping a coded block to obtain a channel hard output block comprising a header hard output and at least one data hard output, de-puncturing and decoding the header hard output to obtain a decoded header part, determining whether the decoded header part has errors, selecting the decoded header part or a decoded whole block as a selected part based on the determination result, wherein the decoded whole block comprises the decoded header part and a decoded data part obtained by de-puncturing and decoding the data hard output, re-encoding the selected part to obtain a re-encoded decision, and comparing the re-encoded decision to the header hard output or the channel hard output corresponding to the selected part to obtain the BEP of the coded block. A receiver employing the BEP estimation method is also provided in the invention. | ||||||
| 75 | First-in/first-out (FIFO) information protection and error detection method and apparatus | US10392626 | 2003-03-20 | US07383492B2 | 2008-06-03 | Philip M. Sailer; Nicholas Paluzzi; Avinash Kallat; Stephen L. Scaringella; Krzysztof Dobecki |
| A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker. | ||||||
| 76 | Semiconductor device having ECC circuit | US10739123 | 2003-12-19 | US07266735B2 | 2007-09-04 | Osamu Hirabayashi |
| A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit which is supplied to an ECC (error connection code) circuit together with remainder bits of the data bits to obtain an error-corrected data which is then supplied to a BIST (Built-In-Self-Test) circuit for testing the error-corrected data obtained from the ECC circuit. | ||||||
| 77 | Modeling error correction capability with estimation of defect parameters | US11261037 | 2005-10-28 | US20070101213A1 | 2007-05-03 | Paul Seger |
| A method, system and program product accurately model the error characteristics of a communications system, such as a tape storage system. Input parameters are entered which describe defect rates and sizes, Codeword Data Structure bytes, and any interleaving factor. Bit defects from simulated defect sources are generated, defined by the starting and ending bits of each defect within a codeword. Any codewords which are defect-free are filtered out and not processed further, thereby increasing the processing speed of the model. Within the defect streams, overlapping defects are merged, redefining defect regions by starting and ending bits. Because only the definitions are processed, not the entire length of the codewords or defects, processing efficiency is further enhanced. The number of defects that occur in each codeword is determined and the probability of the occurrence of N bytes in error per processed codeword may be computed. If desired, a histogram may be generated which includes the rate at which errors occurred and subsequently used to estimate the probability of an error event. Such information may then be incorporated into the design of an error correction code for the modeled system. | ||||||
| 78 | Method and apparatus for recovery of particular bits of a frame | US09588072 | 2000-06-05 | US07159164B1 | 2007-01-02 | Ahmed Saifuddin; Joseph P. Odenwalder; Yu-Cheun Jou; Edward G. Tiedemann, Jr. |
| A method and an apparatus for recovery of particular bits in a frame are disclosed. An origination station forms a frame structure with groups of information bits of different importance. All the information bits are then protected by an outer quality metric. Additionally, the groups of more important information bits are further protected by an inner quality metric; each group having a corresponding quality metric. The frame is then transmitted to a destination station. The destination station decodes the received frame and decides, first in accordance with the outer quality metric, whether the frame has been correctly received, or whether the frame is erased. If the frame has been declared erased, the destination station attempts to recover the groups of more important information bits in accordance with the corresponding inner quality metrics. | ||||||
| 79 | Method and apparatus for generating bit errors in a forward error correction (FEC) system to estimate power dissipation characteristics of the system | US10366250 | 2003-02-13 | US07073117B1 | 2006-07-04 | Howard H. Ireland; Jeffery T. Nichols |
| A method and apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system in order to estimate power dissipation. In accordance with the present invention, it has been determined that a burst error generator that is capable of erroring the maximum number of correctable data bits in every FEC encoded frame, which allows the designer to accurately produce test vectors that are suitable for use in commercially available power estimation tools. In addition, after the IC is produced, the burst error generator of the present invention can be enabled to provide real-time FEC power dissipation data for use in system thermal modeling, thus obviating the need to use costly external devices that emulate a given error rate. Furthermore, the power dissipation data obtained in real-time may be used to refine the initial design power estimate, which will then allow the designer to develop a more accurate prediction of power consumption for future IC designs. Thus, the burst error generator of the present invention is capable of reducing iterations of IC designs by accurately estimating the worst-case power dissipation of FEC decoders. | ||||||
| 80 | Method and apparatus for propagating error status over an ECC protected channel | US10617541 | 2003-07-10 | US07020810B2 | 2006-03-28 | Thomas J. Holman |
| System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted. | ||||||
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