ECC circuit failure verifier |
|||||||
| 申请号 | EP87113099.3 | 申请日 | 1987-09-08 | 公开(公告)号 | EP0265639A3 | 公开(公告)日 | 1991-01-16 |
| 申请人 | International Business Machines Corporation; | 发明人 | Aichelmann, Frederick John, Jr.; | ||||
| 摘要 | A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones. In one embodiment, the circuit comprises for generating a parity bit, P k , for each of K data fields in the ECC word; for comparing logical combinations of these parity bits to logical combinations of the memory check bits, C j , to form H bits; and for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non carry) sum of the syndrome bits to detect syndrome generation path failures. This D bit may also be used to determine if the data bits in an ECC word are correct, a number of cycles before the completion of the normal ECC operation. | ||||||
| 权利要求 | |||||||
| 说明书全文 | |||||||
QQ群二维码
意见反馈
意见反馈