| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | Method and apparatus for calibrating data-dependent noise prediction | US11109207 | 2005-04-18 | US20050180288A1 | 2005-08-18 | Jonathan Ashley; Heinrich Stockmanns |
| Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A-D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps [t2[k], t1[k], t0[k]]of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix C[k] defined by Cij[k]=E(ni-3nj-3|NRZ condition k). | ||||||
| 122 | Semiconductor device having ECC circuit | US10739123 | 2003-12-19 | US20050086572A1 | 2005-04-21 | Osamu Hirabayashi |
| A semiconductor device includes a memory which stores data, an ECC circuit which corrects a bit error of data read out from the memory and generates correction data, a BIST circuit which tests the correction data output from the ECC circuit, and a pseudo error generator circuit which generates a pseudo error for at least one bit configuring the data read out from the memory and supplies the pseudo error to the ECC circuit in a test mode. | ||||||
| 123 | Evaluating and optimizing error-correcting codes using a renormalization group transformation | US09858358 | 2001-05-16 | US06857097B2 | 2005-02-15 | Jonathan S. Yedidia; Jean-Philippe M. Bouchaud |
| A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes. By evaluating many error-correcting codes according to the method, an optimal code according to selected criteria can be obtained. | ||||||
| 124 | Evaluating and optimizing error-correcting codes using projective analysis | US09968182 | 2001-10-01 | US06842872B2 | 2005-01-11 | Jonathan S. Yedida; Erik B. Sudderth; Jean-Philippe Bouchaud |
| A method evaluates and optimizes an error-correcting code to be transmitted through a noisy channel and to be decoded by an iterative message-passing decoder. The error-correcting code is represented by a parity check matrix which is modeled as a bipartite graph having variable nodes and check nodes. A set of message passing rules is provided for the decoder. The decoder is analyzed to obtain a set of density evolution rules including operators and operands which are then transformed to projective operators and projected operands to generate a set of projective message passing rules. The projective message passing rules are applied iteratively to the error-correcting code modeled by the bipartite graph until a termination condition is reached. Error rates of selected bits of the error-correcting code are then determined by evaluating the corresponding operands. The error rates can be passed to an optimizer to optimize the error-correcting code. | ||||||
| 125 | Method of estimating reliability of decoded message bits | US10847285 | 2004-05-18 | US20040243903A1 | 2004-12-02 | Ju Yan Pan; Chang Qing Xu; Masayuki Tomisawa |
| A method of estimating the reliability of decoded message bits in a digital communications system is proposed. Message and tail bits are coded and transmitted across a communications channel. The coded message and tail bits are then decoded and it is determined that the decoded message bits have no error when the decoded tail bits have at least one error. | ||||||
| 126 | First-in/first-out (FIFO) information protection and error detection method and apparatus | US10392626 | 2003-03-20 | US20040187053A1 | 2004-09-23 | Philip M. Sailer; Nicholas Paluzzi; Avinash Kallat; Stephen L. Scaringella; Krzysztof Dobecki |
| A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker | ||||||
| 127 | Encoding rate detection method and encoding rate detection device | US09831636 | 2001-05-11 | US06728926B1 | 2004-04-27 | Takashi Kakemizu; Takehiro Kamada; Yuji Nakai |
| In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded signal (ST11) is generated and then it is judged whether or not synchronization is determined for the first decoded signal (ST12). If the synchronization cannot be determined, there is generated only a second synchronizing signal having a frequency corresponding to a second rate having a difference between itself and a first rate which is smaller than a permissible value of the rate determined by the lower and upper values of the rate (ST13, ST17). | ||||||
| 128 | Method and apparatus for testing a high speed data receiver for jitter tolerance | US10228909 | 2002-08-27 | US20040044948A1 | 2004-03-04 | Charles E. Moore; Aaron M. Volz |
| A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a result, the jitter tolerance of the device under test is measured. | ||||||
| 129 | Method and apparatus for calibrating data-dependent noise prediction | US10402033 | 2003-03-28 | US20040032683A1 | 2004-02-19 | Jonathan J. Ashley; Heinrich J. Stockmanns |
| Disclosed herein is an apparatus and method of calibrating the parameters of a Viterbi detector 138 in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. An offline algorithm for calculating the parameters of data-dependent noise predictive filters 304A-D is presented which has two phases: a noise statistics estimation or training phase, and a filter calculation phase. During the training phase, products of pairs of noise samples are accumulated in order to estimate the noise correlations. Further, the results of the training phase are used to estimate how wide (in bits) the noise correlation accumulation registers need to be. The taps nullt2nullknull, t1nullknull, t0nullknullnull of each FIR filter are calculated based on estimates of the entries of a 3-by-3 conditional noise correlation matrix Cnullknull defined by CijnullknullnullE(ninull3njnull3nullNRZ condition k). | ||||||
| 130 | Method and apparatus for propagating error status over an ECC protected channel | US09725221 | 2000-11-29 | US06622268B2 | 2003-09-16 | Thomas J. Holman |
| System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted. | ||||||
| 131 | Signal evaluation apparatus and signal evaluation method | US10307610 | 2002-12-02 | US20030135812A1 | 2003-07-17 | Jun Akiyama; Tetsuya Okumura |
| There is provided a signal evaluation apparatus and signal evaluation method capable of consistently measuring an accurate bit error rate regardless of the distribution profile of the difference of likelihoods (difference metrics) of data sequences. In the signal evaluation apparatus for decoding data sequences by means of maximum likelihood decoding, at least one pair of paths between which a distance has a minimum value are selected by a path selector circuit 10. With regard to the paths selected by the path selector circuit 10, a difference metric obtained by a difference metric calculator circuit 9 is statistically processed by a null- and null-calculator circuit 13 to calculate a bit error rate. Then, the bit error rate is corrected by correction means (11, 12, 14) on the basis of the number of measurement samples of the paths selected by the path selector circuit 10 and the number of all samples. | ||||||
| 132 | Operating circuit for galois field | US46853 | 1993-04-15 | US5414719A | 1995-05-09 | Tetsuo Iwaki; Toshihisa Tanaka; Eiji Yamada |
| An operating circuit of a Galois Field for executing an operation of the Galois field efficiently and rapidly includes an operating circuit (11) for receiving two elements of a Galois field, for performing an addition or a multiplication of the two elements, and for outputting a first operational result, an operating circuit (12) for receiving another two elements of the Galois field, for performing an addition or a multiplication of another two elements, and for outputting a second operational result, an operating circuit (13) for performing an addition of the first operational result and the second operational result on the Galois field, and for outputting a third operational result, a multiplexer (14) for selecting and one of the first operational result and the third operational result, and for outputting a selected result, a multiplexer (15) for selecting any one of the second operational result and the third operational result, and for outputting the selected result, a flag-decision circuit (18) for determining the first operational result and the second operational result as well as the third operational result. | ||||||
| 133 | Packet start detection using check bit coding | US939806 | 1992-09-03 | US5400348A | 1995-03-21 | Sung-Moon Yang |
| In a digital radio system, data is transmitted in packet form. A check or parity bit is used to determine whether any errors have occurred between data transmission and demodulation. That same check bit is used to identify its location in a packet. From that check bit location, it is then possible to identify the starting and ending data bits in a packet and to correctly interpret the packet data. | ||||||
| 134 | Fault judging device comprising a compression circuit for compressing output pattern signals of a circuit model | US785820 | 1991-10-31 | US5353289A | 1994-10-04 | Kenzo Ohkawa |
| In a fault judging device for use in simulating a circuit model which is defined by a fault data signal indicative of one of circuit elements in the circuit model and which is operable in response to first through n-th input pattern signals to produce first through n-th output pattern signals, a compression circuit compresses the first through the n-th output pattern signals by cyclic coding to produce a compressed signal represented by a cyclic code sequence. A comparator compares the cyclic code sequence with a specific code sequence which defines a normal circuit related to the circuit model. The comparator produces a comparison result signal, as a judging result signal, representative of fault of one of the circuit elements when the cyclic code sequence does not coincide with the specific cyclic code sequence. | ||||||
| 135 | Viterbi decoder and method for testing the viterbi decoder | US919698 | 1986-10-16 | US4763328A | 1988-08-09 | Kaneyasu Shimoda; Atsushi Yamashita; Tadayoshi Katoh |
| An integrated viterbi decoder structure and method, the viterbi decoder receives test input signals at a distributor, an ACS circuit and a path memory and compares the output signals generated by the test input signals with predetermined test signals so as to test the internal operations of the viterbi decoder without the need for complex logic housed with the viterbi decoder. | ||||||
| 136 | ECC circuit failure detector/quick word verifier | US923522 | 1986-10-27 | US4740968A | 1988-04-26 | Frederick J. Aichelmann, Jr. |
| A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones.In one embodiment, the circuit comprises means for generating a parity bit, P.sub.k, for each of K data fields in the ECC word; means for comparing logical combinations of these parity bits to logical combinations of the memory check bits, C.sub.j, to form H bits; and means for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non-carry) sum of the syndrome bits to detect syndrome generation path failures. This D bit may also be used to determine if the data bits in an ECC word are correct, a number of cycles before the completion of the normal ECC operation. | ||||||
| 137 | Parallel cyclic redundancy checking circuit | US411203 | 1982-08-25 | US4454600A | 1984-06-12 | Barry P. LeGresley |
| A parallel cyclic redundancy checking circuit which determines the validity of digital, binary, cyclical data. The parallel structure of this circuit enables it to check high frequency data. Shift registers store sequentially occurring parallel groups of data and a feedback network comprising exclusive-or gates provides a coding arrangement which produces a resultant data pattern to indicate the validity of the cyclical parallel input data. Resultant data patterns are periodically stored in a random-access-memory which initializes the shift registers to provide a time sharing operation. A comparator detects invalid data by comparing the resultant patterns with expected values. | ||||||
| 138 | VOICE QUALITY MONITORING SYSTEM | EP16726688.1 | 2016-05-05 | EP3292674A1 | 2018-03-14 | KIM, Doh-Suk |
| This disclosure falls into the field of voice communication systems, more specifically it is related to the field of voice quality estimation in a packet based voice communication system. In particular the disclosure provides methods, computer program products and devices for reducing a prediction error of the voice quality estimation by considering forward error correction of lost voice packets. | ||||||
| 139 | SECURE COMMUNICATION USING NON-SYSTEMATIC ERROR CONTROL CODES | EP09819869.0 | 2009-10-08 | EP2344985A1 | 2011-07-20 | MCLAUGHLIN, Steven, William; KLINC, Demijan; HA, Jeongseok |
| A transmitter device (110T) for secure communication includes: an encoder (170) configured to apply a non-systematic error correcting code (NS ECC) to a message, thus producing encoded bits with no clear message bits; and a transceiver (720) configured to transmit the encoded bits over a main channel to a receiver. A method for secure communication includes: encoding a message with an NS ECC to produce an encoded message carrying no message bits in the clear; and transmitting the encoded message over a main channel (120). The NS ECC characteristics result in an eavesdropper channel error probability under a security threshold (320) and a main channel error probability over a reliability threshold (310), whenever an eavesdropper (140) listening on an eavesdropper channel (150) is more than distance Z (220) from the transmitter. Unreliable bits in the encoded bits render the eavesdropper unable to reliably decode messages on the main channel. | ||||||
| 140 | Evaluating and optimizing error-correcting codes using a renormalization group transformation | EP02009144.3 | 2002-04-24 | EP1258999A2 | 2002-11-20 | Yedidia, Jonathan S.; Bouchaud, Jean-Philippe M. |
A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes. By evaluating many error-correcting codes according to the method, an optimal code according to selected criteria can be obtained. |
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