| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 241 | JPS5086966A - | JP13551873 | 1973-11-30 | JPS5086966A | 1975-07-12 | |
| 242 | 逐次比較型Ａ／Ｄ変換装置 | JP2017524159 | 2015-06-15 | JPWO2016203522A1 | 2018-04-05 | 平出 修三 |
| 容量回路の容量が変動しても、デジタル信号のフルスケールレンジを確保することができる逐次比較型A/D変換回路を提供する。逐次比較型A/D変換装置は、差動入力信号を構成する1対のアナログ信号をサンプリングするサンプリング回路(110)と、減衰容量部(CHP,CHN)およびバイナリ容量部(C0P〜C7P,C0N〜C7N)を有し、前記減衰容量部(CHP,CHN)およびバイナリ容量部(C0P〜C7P,C0N〜C7N)を介して前記1対のアナログ信号に基準信号の信号レベルを反映させることにより1対の電圧信号を発生させる容量回路(121)とを備える。前記減衰容量部(CHP,CHN)は、前記サンプリングされたアナログ信号が保持される信号ノードと所定電位ノードとの間に接続された固定容量部と、前記固定容量部と並列接続された可変容量部とを備える。 | ||||||
| 243 | D/A変換器、及びA/D変換器 | JP2016040764 | 2016-03-03 | JP2017158074A | 2017-09-07 | 井上 文裕; 茂木 朗 |
| 【課題】オーバーサンプリングの回数を抑制しつつ、DEMによる誤差を低減させるD/Aコンバータを提供する。 【解決手段】D/A変換器10は、所定のビット数のデジタル信号をアナログ信号に変換するD/A変換器10であって、前記D/A変換器10を構成する複数の構成要素を含み、前記アナログ信号を出力する出力部130に所定の順序で接続された複数の構成要素群110と、前記デジタル信号に対応するひとつのアナログ信号を生成するときに、前記ひとつのアナログ信号の生成に用いる前記複数の構成要素群110のスタート位置を、予め定められたシフトパターンを用いて変更するスタート位置変更部121と、を有する。 【選択図】図1 |
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| 244 | A/D変換回路 | JP2015083317 | 2015-04-15 | JP2016001869A | 2016-01-07 | 谷澤 幸彦 |
| 【課題】デジタル演算を行うことなくアナログ入力電圧の非直線性を補正する。 【解決手段】信号比率変更回路2は、基準電圧Vrefに、差分電圧ΔV(=アナログ入力電圧Vin−基準電圧Vref)に比例した第1差分電圧を加算した電圧(=Vref+A1・ΔV)を電源線7に出力し、基準電圧Vrefから、差分電圧ΔVに比例し且つ第1差分電圧とは絶対値が異なる第2差分電圧を減算した電圧(=Vref−A2・ΔV)を電源線8に出力する。第1パルス周回回路31は電源線7およびグランド線9から電源電圧の供給を受け、第2パルス周回回路32は電源線8およびグランド線9から電源電圧の供給を受ける。周回数差計測部3はパルス周回回路31、32のパルス周回数差を出力する。変換制御回路4は、パルス周回回路31、32を同時に周回動作させ、変換データ出力処理信号Saを出力した時の周回数差計測部3の出力値をA/D変換データとして出力する。 【選択図】図1 |
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| 245 | Sensor signal processing device and sensor device | JP2013016878 | 2013-01-31 | JP2014150338A | 2014-08-21 | TANIZAWA YUKIHIKO |
| PROBLEM TO BE SOLVED: To shorten a time from the start of A/D conversion of a sensor signal to the output of A/D conversion data with temperature characteristics of a physical quantity sensor canceled.SOLUTION: A sensor signal processing device includes a first A/D converter 7 having a variable offset and conversion gain and configured to A/D-convert a sensor signal of a physical quantity sensor 2, and a second A/D converter 8 configured to A/D-convert a temperature signal of a temperature sensor 3 for sensing a temperature of the physical quantity sensor 2. A temperature measurement process of instructing the A/D converter 8 to execute A/D conversion of the temperature signal, an arithmetic process of computing such an offset and conversion gain of the A/D converter 7 so as to cancel temperature characteristics of the physical quantity sensor 2 in the process of the A/D converter 7 A/D-converting the sensor signal, on the basis of an A/D conversion value of the A/D converter 8 and temperature characteristic data on the physical quantity sensor 2, and a signal conversion process of setting the computed offset and conversion gain in the A/D converter 7 to instruct the A/D converter 7 to execute A/D conversion of the sensor signal are executed concurrently. | ||||||
| 246 | System and method for calibrating time interleaved timing of data converter | JP2006128483 | 2006-05-02 | JP2006313162A | 2006-11-16 | FERNANDEZ ANDREW D; SRIKANTAM VAMSI K; NEFF ROBERT M R; POULTON KENNETH D |
| PROBLEM TO BE SOLVED: To provide system and method for faster and low-cost calibration of sampling timing in data conversion system. SOLUTION: This is the method for calibrating time-interleaved sample, comprising a step (102) for impressing calibration signal on time-interleaved sampling device, a step (104) for sampling calibration signal in multiphase by using the time-interleaved sampling device to produce a plurality of samples, a step (106) for averaging those produced samples, and a step (108) for computing phase difference of each sample based on the average calibration signal sample. The calibration signal matches with at least one sampling clock in the sampling device, also being periodic to have prescribed spectral element and frequency. COPYRIGHT: (C)2007,JPO&INPIT | ||||||
| 247 | Method of determining measuring time of a/d converter | JP2000195917 | 2000-06-29 | JP2002014119A | 2002-01-18 | HIRAMATSU TOMONOBU; TANIDA SHINICHI |
| PROBLEM TO BE SOLVED: To reduce the time required for measurement, while keeping resolution, in an A/D converter for measuring a very small electric current. SOLUTION: This measuring time determining method for the A/D converter includes a premeasuring step for preliminarily measuring the current to be measured, a step for determining the voltage range and a current range used for the measurement, and a step for determining the measuring time for the A/D converter for the measurement, based on the determined voltage range, the determined current range and a measured current value. | ||||||
| 248 | JPH023304B2 - | JP16978882 | 1982-09-30 | JPH023304B2 | 1990-01-23 | KUDO KYOICHI |
| 249 | JPH0116060B2 - | JP12723980 | 1980-09-16 | JPH0116060B2 | 1989-03-22 | AKAZAWA YUKIO; MATSUTANI YASUYUKI; IWATA ATSUSHI |
| 250 | JPS6353738B2 - | JP15695083 | 1983-08-26 | JPS6353738B2 | 1988-10-25 | NIIJIMA HIRONOBU; SHIBAYAMA AKINORI |
| 251 | JPS6326927B2 - | JP10813581 | 1981-07-13 | JPS6326927B2 | 1988-06-01 | MATSUTANI YASUYUKI; AKAZAWA YUKIO; IWATA ATSUSHI |
| 252 | JPS634967B2 - | JP12170782 | 1982-07-13 | JPS634967B2 | 1988-02-01 | MATSUTANI YASUYUKI; AKAZAWA YUKIO; IWATA ATSUSHI |
| 253 | Noise eliminatng method of analog-to-digital converter | JP5897684 | 1984-03-27 | JPS60203020A | 1985-10-14 | SAGARA TADAO |
| PURPOSE:To eliminate the periodical noises of an A/D converter by providing a noise memory to store the noise signal of the output of the A/D converter in a state where no input signal exists. CONSTITUTION:An A/D converter 10 delivers the periodical noises in a state where the converter 10 has no input, and the periodical noises are stored in a noise memory 12. While the converter 10 delivers a digital signal containing the noise component when the converter 10 has an input signal. The output signal of the converter 10 is supplied to a subtractor circuit 14 together with the periodical noise read out of the memory 12. Then the subtraction processing is carried out. Thus the periodical noises can be eliminated for the converter 10. | ||||||
| 254 | Analog-digital converting circuit device | JP5380584 | 1984-03-21 | JPS60197016A | 1985-10-05 | NISHIKAWA AKINARI |
| PURPOSE:To eliminate a DC offset portion, and to digitize exactly an analog signal by adding an offset detecting means and an offset eliminating means. CONSTITUTION:An analog signal A from an input terminal 11 is supplied to an S & H circuit 12 through a variable bias circuit 22. An output of this S & H circuit 12 is supplied to an offset detecting circuit 27 through an ADC circuit 20. Subsequently, offset data detected by the detecting circuit 27 is converted to an analog signal by a DAC circuit 37, and a DC offset voltage of an analog value is obtained. By applying this DC offset voltage to the bias circuit 22 through an inverting circuit 38, a DC offset portion is eliminated from an analog signal A and it is brought to digital conversion. In this way, the DC offset portion is eliminated and the analog signal can be digitized exactly. | ||||||
| 255 | A-d-d-a converter | JP5151584 | 1984-03-16 | JPS60194829A | 1985-10-03 | SANO SHINYA |
| PURPOSE:To decrease a distortion due to error at a zero cross point by adjusting a current value of an MSB of a sequential comparison reference current source equally to the total sum of current values of reference current sources to elminate the need for trimming. CONSTITUTION:A current value of the comparison reference current sources 1- N of a converter 7 is sequentially to I, I/2, I/2<2>-I/2N<-1> and the current value of the MSB is changed so that a voltage difference between an output of a sample hold circuit 16 of the current value of the MSB turning on a switch 3 only and an output of a sample hold circuit 17 of a current total sum of the LSB turning on all switches 4 except the switch 3 is zero. Thus, the erroneous distortion at the zero point of the analog signal is decreased without trimming. | ||||||
| 256 | Digital and analog converter | JP4924984 | 1984-03-16 | JPS60194619A | 1985-10-03 | MORIYA SHIGERU; KOMATSU KAZUHIKO; KITAYAMA TOYOKI; MATSUMOTO MASAAKI |
| PURPOSE:To make self-corrections of a center value and output width in additon to linearity by making an output analog signal after self-calibration of linearity coincident with a reference value corresponding to the output analog signal when an input digital signal is all composed of ''1''s and when only the mos significant digit of the input analog signal is set to ''1''. CONSTITUTION:When a start command is applied to a calibration start command input terminal O, a switch circuit P enters a mode for supplying the output of an amplifier J to a synchronism detector K directly and the self-calibration of the linearity of an output analog signal is performed. Then, the switch circuit P enters a mode for sending out the output of a reference power source R1 and the output of the amplifier J alternately and the output analog signal converges so as to coincide with a reference value corresponding to the output analog signal having only the most significant digit set to ''1''. Then, the switch circuit switches the output of a reference power source R2 and the output of the amplifier J alternately and the output analog signal converges so as to coincide with a reference value corresponding to the output analog signal whose digits are all set to ''1''. | ||||||
| 257 | Pcm system reproducing device | JP2390684 | 1984-02-09 | JPS60165831A | 1985-08-29 | FUKUHARA KOUJI |
| PURPOSE:To eliminate a DC component from an analog signal by detecting the DC component of the analog signal subjected to D/A conversion and feeding back this component into a digital signal to allow a proper processing in the stage of the digital signal before conversion to it. CONSTITUTION:The DC component is detected from an output of a buffer amplifier 8 at a DC component detecting circuit 9, A comparator 10 of the next stage detects the polarity of the said detected output. Then an up-down counter 11 is counted up or down in synchronization with the sampling frequency depending on the polarity of the said detected output and its count output is given to one input of a subtractor circuit 12. An output of a signal processing circuit 1 is given to the other input of the subtractor circuit 12. The subtractor circuit 12 subtracts an output of the counter 11 from the output of the signal processing circuit 1. The DC component generated in an output of the buffer amplifier 8 is eliminated through the said subtraction. | ||||||
| 258 | Test method of microcomputer built in analog circuit | JP23741083 | 1983-12-16 | JPS60128540A | 1985-07-09 | TANIGUCHI YUKIHIRO |
| PURPOSE:To test simply an analog circuit of a device to be measured by a CPU itself by using a storage device operating the said CPU of the device to be measured and a proper external circuit or the like. CONSTITUTION:An A/D converter test program is fetched in advance to a CPU 31 via a connecting line 8. When the CPU31 outputs a digital value to a D/A converter device 9 according to the program, the digital value is converted into an analog value at the D/A converter device 9 and the analog value is inputted to an A/D converter 32 so as to A/D-convert data and compares it with a digital value inputted to the D/A converter device 9 via the connection line 10. Through the comparison above, tie defect of the A/D converter is discriminated. | ||||||
| 259 | Automatic correction signal processor | JP22034583 | 1983-11-22 | JPS60112325A | 1985-06-18 | OGAWA SHIGERU |
| PURPOSE:To omit a potentiometer for control of zero and span and also to attain an automatic correcting job by storing the corrected values of both the zero and span for each point of measurement and calculating the measured value sent from a detector with said corrected value to obtain the corrected measurement value. CONSTITUTION:The input signal of each point of measurement is first set at 0(mV) and applied through each of terminals 11, 12.... A central processor 6 drives S1, S2... of a switch 2 to digitize the data obtained during the input 0(mV) of each point of measurement by an A/D converter 3 to obtain data of alpha1, alpha2.... These data are stored in a memory 7. Then the input signal is set at the span value, and the correction values obtained when the span reference voltage Es(mV) is applied are stored in the memory 7 in the form of beta1 and beta2.... Thus the corrected value is obtained for both zer and span controls. The measurement values obtained by S1, S2... of the switch 2 are corrected by the zero and the span stored in the memory 7 for each point of measurement. Thus the corected measurement value is obtained and displayed on a display device 5 or delivered via an output part 8. | ||||||
| 260 | Synchro digital converter | JP19653283 | 1983-10-20 | JPS6089130A | 1985-05-20 | OONO KOUJI |
| PURPOSE:To improve the reliability of an angular data by comparing a data obtained at first with a converted data again and outputting the result after self- check in a device converting a synchro three-phase data. CONSTITUTION:When a set signal 17 is inputted, external synchro three-phase data 1-3 are inputted to a synchro digital converting circuit 5 via an input control circuit 4. A comparison operating circuit 16 detects the end of conversion by a busy signal 14 and stores the digital data to a memory so as to use it for an input to a digital synchro converting circuit 6. A selection signal 10 is fed to the circuit 4 in this case and output synchro three-phase data 7-9 of the circuit 6 are selected as the input to the circuit 5. The circuit 16 receives again a digital data 15, compares it with a data in the memory and when they are coincident, an output 18 is obtained. | ||||||
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