Input path matching in pipelined continuous-time analog-to-digital converters |
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| 申请号 | US15455971 | 申请日 | 2017-03-10 | 公开(公告)号 | US10084473B2 | 公开(公告)日 | 2018-09-25 |
| 申请人 | Texas Instruments Incorporated; | 发明人 | Venkatesh Srinivasan; Kun Shi; Victoria Wang; Nikolaus Klemmer; | ||||
| 摘要 | System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit. | ||||||
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