| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 61 | 低共模驱动器 | CN201210171148.2 | 2012-05-29 | CN102820859A | 2012-12-12 | 刘慜; 王昕; 查尔斯·清乐·吴 |
| 本发明涉及提供用于高速及低电压共模驱动器的复制偏置电路的技术。在一实施例中，前置驱动器经耦合以将驱动器输入电压提供到驱动器，所述驱动器包含经耦合以基于所述驱动器输入电压提供差分输出的输出信号的一组电路元件。在另一实施例中，调节器电路经耦合以将经调节电力提供到所述前置驱动器及所述驱动器，其中所述调节器电路包含具有第一组电路元件的复制的比例复制电路。 | ||||||
| 62 | 线缆调制解调器节能电路 | CN200910309158.6 | 2009-10-30 | CN102055697A | 2011-05-11 | 张亮; 吴正宇 |
| 一种线缆调制解调器节能电路，其包括电源模块、开关电路，监视模块及双工器及信号收发电路。电源模块包括电源输入端及电源输出端。电源输入端连接在外部电源上。电源输出端连接至一放大器。开关电路包括P-MOS管，第一电子开关。P-MOS管的漏极连接至放大器，源极连接至电源输出端。第一电子开关的集电极连接至P-MOS管的栅极，发射极接地。监视模块包括一监视信号源，该监视信号源连接至第一电子开关的基极。还包括一射频匹配电路。双工器与信号收发电路相电连接。射频匹配电路包括第二电子开关及匹配器件。第二电子开关的基极连接在第一电子开关的集电极上，集电极与双工器连接，发射极连接在匹配器件的一端，另一端接地。 | ||||||
| 63 | 用以适应性地偏置通信系统的可适性偏置电路 | CN201010169914.2 | 2010-05-12 | CN101997495A | 2011-03-30 | 陈志纬; 赵传珍; 王是琦 |
| 本发明提供一种可适性偏置电路，用以提供对输入功率更灵敏的可适性偏置电流给电子电路，可适性偏置电路包括第一晶体管耦接至供应电源，电压偏置电路耦接至该第一晶体管和该供应电源用以偏置该第一晶体管，和第一耦合模块耦接至该第一晶体管和该电子电路用以耦合输入信号能量的一部分至该第一晶体管。第二晶体管是耦接至该第一晶体管和该供应电源以增加该可适性偏置电路的电流增益，和第二耦合模块是耦接至该第二晶体管和该电子电路以提供可适性偏置电流至该电子电路。 | ||||||
| 64 | METHOD AND APPARATUS FOR A MULTI-STANDARD, MULTI-MODE, DYNAMIC, DC-DC CONVERTER FOR RADIO FREQUENCY POWER AMPLIFIERS | PCT/IB2014059529 | 2014-03-07 | WO2014125464A3 | 2015-01-08 | ARNO PATRIK; THOMAS MATTHIEU |
| A multi-mode, dynamic, DC-DC converter supplies a dynamically varying voltage, as required, from a battery to an RF power amplifier (PA). In envelope tracking mode, a fast DC- DC converter generates a dynamic voltage that varies based on the amplitude envelope of an RF signal, and regulates the voltage at the PA. A slow DC-DC converter generates a steady voltage and regulates the voltage across a link capacitor. The fast and slow converters are in parallel from the view of the PA, and the link capacitor is between the fast converter and the PA. Because different nodes are regulated, no current sharing is possible between the converters. The link capacitor boosts the dynamic voltage level, allowing a maximum dynamic voltage at the load to exceed the battery voltage. In power level tracking mode, the fast converter is disabled and the link capacitor is configured to be in parallel with the load. The slow converter directly regulates the PA, and the link capacitor is in parallel with (added to) an output capacitor. Multiple wireless network standards may be supported, allowing for the sharing of RF circuits. | ||||||
| 65 | SYSTEM AND METHOD FOR BIASING A POWER AMPLIFIER | PCT/US2011046971 | 2011-08-08 | WO2012021461A3 | 2012-06-28 | GREEN DUANE A; SHU WEIWEI; SAWATZKY DAVID |
| A system and method for biasing a power amplifier includes a power amplifier having a driver stage and an output stage, the driver stage having a plurality of driver devices, a bias current source configured to deliver a bias current to each of the plurality of driver devices, and a current directing element configured to receive the bias current and selectively bias each of the plurality of driver devices based on a reference voltage and a system voltage. | ||||||
| 66 | 偏置电路 | CN201720379473.6 | 2017-04-12 | CN206775475U | 2017-12-19 | 田中聪; 安达彻朗; 渡边一雄; 沼波雅仁; 山本靖久 |
| 本实用新型提供一种与输入信号的信号电平无关而稳定地提供偏置电流的偏置电路。偏置电路向对无线频率信号进行放大的放大器提供第1偏置电流或电压，其包括：FET，该FET的漏极被提供有电源电压，从源极输出第1偏置电流或电压；第1双极型晶体管，该第1双极型晶体管的集电极与FET的栅极相连接，基极与FET的源极相连接，发射极接地，且集电极被提供有恒定电流；以及第1电容器，该第1电容器的一端与第1双极型晶体管的集电极相连接，并抑制第1双极型晶体管的集电极电压的变动。 | ||||||
| 67 | ENVELOPE TRACKING WITH LOW FREQUENCY LOSS CORRECTION | EP15178690.2 | 2015-07-28 | EP2980988B1 | 2018-12-26 | BALTEANU, Florinel G.; MACEDO, Jose Alejandro; PINGOT, Jakub F.; POPPLEWELL, Peter Harris Robert |
| A low frequency loss correction circuit that improves the efficiency of a power amplifier at near-DC low frequencies The low frequency loss correction circuit can include a signal error detection circuit configured to produce an error signal in response to detecting one or more frequency components of a tracking signal below a cutoff frequency that are substantially attenuated through a capacitive path. The low frequency loss correction circuit can include a drive circuit configured to convert the error signal into a low frequency correction signal, and provide the low frequency correction signal to a voltage supply line, the low frequency correction signal including at least some of the one or more frequency components of the tracking signal below a cutoff frequency that are substantially attenuated through the capacitive path. | ||||||
| 68 | SEMICONDUCTOR AMPLIFIER BIAS CIRCUIT AND SEMICONDUCTOR AMPLIFIER DEVICE | EP15175539.4 | 2015-07-06 | EP3016281B1 | 2018-08-22 | TAKAGI, Kazutaka |
| A semiconductor bias circuit (34) includes a first transmission line (40), a second transmission line (30), means for grounding a fundamental signal and a power supply terminal (39). The second transmission line (30) has an electrical length of 90° at a center frequency of a band. The means for grounding a fundamental signal includes one of a grounded shunt capacitor (32) and an open stub line (31) having an electrical length of 90°. In case of the means including the grounded shunt capacitor (32), the second transmission line (30) includes one end part connected to the first transmission line (40) at a position apart from the output end part (19) by an electrical length of 45°, and the other end part connected to the grounded shunt capacitor (32). In case of the means including the open stub line (31), the open stub line (31) includes one end part connected the second transmission line (30), and other end part made open. | ||||||
| 69 | HIGH BANDWIDTH POWER SUPPLY SYSTEM WITH HIGH EFFICIENCY AND LOW DISTORTION | EP10802603.0 | 2010-06-18 | EP2457133B1 | 2018-08-08 | JENSEN, Brent, Roger; DROGI, Serge, Francois; TOMASZ, Martin |
| A power supply system uses improved Class G amplifier architecture for high bandwidth operation with low distortion. The power supply system switches between multiple power supply rails, depending on the signal level handled by the power supply system. The lowest usable supply rail voltage is chosen to minimize power dissipation in the output driver, thus optimizing efficiency. Each supply rail has an associated driver capable of sourcing current to the amplifier output. When a supply rail is selected, its associated driver is enabled and other driver(s) not associated with the selected supply rail are disabled via separate disable control signals. The disabling of the deselected driver may be delayed until current above a predetermined threshold is sensed at the output of the enabled driver. In addition, the frequency of switching between the power rails may be limited via various means designed to limit distortion in the power supply system. | ||||||
| 70 | Pseudo-envelope following power management system | EP14162658.0 | 2011-04-19 | EP2782246B1 | 2018-06-13 | Khlat, Nadim; Kay, Michael, R. |
| Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier. | ||||||
| 71 | AMPLIFIER CIRCUIT AND AMPLIFIER CIRCUIT IC CHIP | EP14814595.6 | 2014-06-17 | EP3012971B1 | 2017-10-11 | OGAWA, Tomohiko; KOIZUMI, Yoshihiko |
| The present disclosure is related to an amplifier circuit in which noise components are reduced to achieve a high SN ratio, a low noise, and a small area, and an amplifier circuit IC chip. An amplifier circuit (100) includes a converter (70) configured to convert a predefined physical quantity to a resistance value, and the resistance value converted by the converter (70) is converted to a voltage value and then amplified. The converter (70) includes variable resistance sensors (71, 72) of piezoresistance elements. A bias unit (80) is configured to determine a bias current of the converter (70), and includes bias resistances (81, 82). An operation amplifier unit (90) receives, as input signals, output signals from the bias unit (80) and the converter (70), and includes feedback resistances (91, 92) respectively connected to input and output ends of a first operational amplifier (101). The first operational amplifier (101) is a whole differential operational amplifier including a common-mode feedback circuit. | ||||||
| 72 | SUPPLY MODULATION FOR RADIO FREQUENCY POWER AMPLIFICATION | EP15797554.1 | 2015-11-10 | EP3221962A1 | 2017-09-27 | WANG, Zhancang |
| The subject matter described herein relates to supply modulation for power amplification. In one embodiment, the voltage level of the envelope with a tunable threshold voltage. The high level part of the envelope above the threshold voltage is maintained and amplified, for example, by the linear amplification process. On the other hand, the low level part of the envelope is replaced with the constant low voltage level. In amplification, the shaped low level part can be prompted to the predefined low supply voltage which may be directly output to the RFPA. By eliminating complicated amplification process on the lower level part of the envelope, the efficiency and bandwidth of the supply modulation can be improved and the circuitry can be simplified, without introducing any timing mismatch or delays. | ||||||
| 73 | CIRCUITS AND METHODS FOR REDUCING SUPPLY SENSITIVITY IN A POWER AMPLIFIER | EP15784905.0 | 2015-10-13 | EP3210298A1 | 2017-08-30 | SCUDERI, Antonino; HADJICHRISTOS, Aristotele |
| In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range. | ||||||
| 74 | AMPLIFIER SYSTEM, CONTROLLER OF MAIN AMPLIFIER AND ASSOCIATED CONTROL METHOD | EP16185674.5 | 2016-08-25 | EP3168986A1 | 2017-05-17 | LIN, Lai-Ching; TSAI, Ming-Da |
The present invention provides a control circuit (1 20) to stabilize an output power of a power amplifier (110). The control circuit (120) comprises a voltage clamping loop (1 30), a current clamping loop (140) and a loop (1 50) for reducing power variation under VSWR, where the voltage clamping loop (1 30) is used to clamp an output voltage of the power amplifier (110) within a defined voltage range, the current clamping loop (140) is used to clamp a current of the power amplifier (110) within a defined current range, and the loop (1 50) for reducing power variation under VSWR is implemented by an impedance detector (1 50) to compensate the output power under VSWR variation.
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| 75 | POWER AMPLIFICATION DEVICE AND METHOD | EP14855915 | 2014-09-29 | EP3062440A4 | 2017-04-19 | YANG DONG-IL |
| Various embodiments of the present invention relate to a power amplification device and method, wherein the power amplification device can comprise: a power amplifier; a switch mode converter for controlling a bias of the power amplifier; a comparator for providing a switching signal to the switch mode converter according to an envelope signal; and a control unit for determining whether a switching frequency of the switch mode converter is within a specific band and applying an offset to the switching frequency so as to deviate from the specific band if the switching frequency of the switch mode converter is within the specific band. Various other embodiments can be carried out. | ||||||
| 76 | POWER AMPLIFIER WITH INPUT POWER PROTECTION CIRCUITS | EP14822702 | 2014-07-09 | EP3020129A4 | 2017-03-15 | GORBACHOV OLEKSANDR; ZHAO HUAN; ZHANG LISETTE L; MUSIOL LOTHAR; QIAN YONGXI |
| An RF power amplifier circuit and input power limiter circuits are disclosed. A power detector generates a voltage output proportional to a power level of an input signal. There is a directional coupler with a first port connected to a transmit signal input, a second port connected to the input matching network, and a third port connected to the power detector. A first power amplifier stage with an input is connected to the input matching network and an output is connected to the transmit signal output. A control circuit connected to the power detector generates a gain reduction signal based upon a comparison of the voltage output from the power detector to predefined voltage levels corresponding to specific power levels of the input signal. Overall gain of the RF power amplifier circuit is reduced based upon the gain reduction signal that adjusts the configurations of the circuit components. | ||||||
| 77 | AMPLIFIER CIRCUIT AND AMPLIFIER-CIRCUIT CHIP | EP14814595 | 2014-06-17 | EP3012971A4 | 2016-11-30 | OGAWA TOMOHIKO; KOIZUMI YOSHIHIKO |
| The present disclosure is related to an amplifier circuit in which noise components are reduced to achieve a high SN ratio, a low noise, and a small area, and an amplifier circuit IC chip. An amplifier circuit (100) includes a converter (70) configured to convert a predefined physical quantity to a resistance value, and the resistance value converted by the converter (70) is converted to a voltage value and then amplified. The converter (70) includes variable resistance sensors (71, 72) of piezoresistance elements. A bias unit (80) is configured to determine a bias current of the converter (70), and includes bias resistances (81, 82). An operation amplifier unit (90) receives, as input signals, output signals from the bias unit (80) and the converter (70), and includes feedback resistances (91, 92) respectively connected to input and output ends of a first operational amplifier (101). The first operational amplifier (101) is a whole differential operational amplifier including a common-mode feedback circuit. | ||||||
| 78 | OPERATIONAL AMPLIFIER BASED CIRCUIT WITH COMPENSATION CIRCUIT BLOCK USED FOR STABILITY COMPENSATION | EP15191878.6 | 2015-10-28 | EP3021482A1 | 2016-05-18 | Yu, Chi-Yao |
An operational amplifier based circuit (100) has an operational amplifier (102), a feedback circuit (104), and a compensation circuit block (106). The feedback circuit (104) is coupled between an output port and an input port of the operational amplifier (102). The compensation circuit block (106) has circuits involved in stability compensation of the operational amplifier (102), wherein there is no stability compensation circuit driven at the output port of the operational amplifier (102).
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| 79 | POWER AMPLIFIER MODULES INCLUDING RELATED SYSTEMS, DEVICES, AND METHODS | EP13805010 | 2013-06-13 | EP2862273A4 | 2016-04-13 | CHEN HOWARD E; GUO YIFAN; HOANG DINHPHUOC VU; JANANI MEHRAN; KO TIN MYINT; LEHTOLA PHILIP JOHN; LOBIANCO ANTHONY JAMES; MODI HARDIK BHUPENDRA; NGUYEN HOANG MONG; OZALAS MATTHEW THOMAS; PETTY-WEEKS SANDRA LOUISE; READ MATTHEW SEAN; RIEGE JENS ALBRECHT; RIPLEY DAVID STEVEN; SHAO HONGXIAO; SHEN HONG; SUN WEIMIN; SUN HSIANG-CHIH; WELCH PATRICK LAWRENCE; ZAMPARDI PETER J JR; ZHANG GUOHAO |
| A system for biasing a power amplifier module, where the module comprises:a first die (409) including a power amplifier circuit (415) and a passive component (412)having an electrical property that depends on one or more conditions of the first die, anda second die (414) including a bias signal generating circuit (413) that is configured to generate a bias signal based at least in part on measurement of the electrical property of the passive component of the first die. | ||||||
| 80 | REDUCING KICKBACK CURRENT TO POWER SUPPLY DURING CHARGE PUMP MODE TRANSITIONS | EP14797482.8 | 2014-05-12 | EP2997432A1 | 2016-03-23 | THANDRI, Bharath, Kumar; NGUYEN, Thuan, L.; ALLEN, Daniel, John; ZHANG, Lingli; SATOSKAR, Aniruddha; BRENNAN, Aaron; SHEN, Dan |
| Kickback current from a charge pump to a power management integrated circuit (PMIC) may be reduced by dissipating charge from fly and hold capacitors during mode transitions. A switch may be placed in series between the charge pump and the PMIC to disconnect the charge pump and prevent kickback current from reaching the PMIC. Further, additional loads, as switches, may be coupled to the charge pump outputs to dissipate charge from the fly and hold capacitors. Additionally, a closed feedback loop may be used to monitor and discharge excess charge from the fly and hold capacitors during mode transitions. Furthermore, charge may be redistributed between the fly and hold capacitors during mode transitions to reduce the time period of the transition. | ||||||
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