| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | COMMUNICATIONS BASED ADJUSTMENTS OF AN ENVELOPE TRACKING POWER SUPPLY | PCT/US2014012927 | 2014-01-24 | WO2014116933A3 | 2014-11-20 | KHLAT NADIM; KAY MICHAEL R; NAG MANBIR SINGH |
| A parallel amplifier and a parallel amplifier power supply are disclosed according to one embodiment of the present disclosure. The parallel amplifier power supply provides a parallel amplifier power supply signal, which is adjustable on a communications slot-to-communications slot basis. During envelope tracking, the parallel amplifier regulates an envelope power supply voltage based on the parallel amplifier power supply signal. The parallel amplifier and an offset capacitance voltage control loop are disclosed according to an alternate embodiment of the present disclosure. The parallel amplifier has a parallel amplifier output, which is coupled to an envelope tracking power supply output via an offset capacitive element. The offset capacitive element has an offset capacitive voltage. The offset capacitance voltage control loop regulates the offset capacitive voltage, which is adjustable on a communications slot-to-communications slot basis. | ||||||
| 182 | PROGRAMMABLE RF NOTCH FILTER FOR ENVELOPE TRACKING | PCT/US2013052277 | 2013-07-26 | WO2014018861A4 | 2014-04-24 | KHLAT NADIM |
| A parallel amplifier (14), a switching supply (12), and a radio frequency (RF) notch filter (18) are disclosed. The parallel amplifier has a parallel amplifier output, such that the switching supply is coupled to the parallel amplifier output. Further, the RF notch filter is coupled between the parallel amplifier output and a ground. The RF notch filter has a selectable notch frequency, which is based on an RF duplex frequency. | ||||||
| 183 | RADIO FREQUENCY COMMUNICATIONS SYSTEM | PCT/US2011050633 | 2011-09-07 | WO2012033801A3 | 2013-05-02 | LEVESQUE CHRIS; BERCHTOLD JEAN-CHRISTOPHE; COLLES JOSEPH HUBERT; DEUCHARS ROBERT; SOUTHCOMBE WILLIAM DAVID; ZIMLICH DAVID; JONES DAVID E; YODER SCOTT; STOCKERT TERRY J |
| The present disclosure relates to a radio frequency (RF) communications system, which may include any or all of RF modulation and control circuitry, RF power amplifier (PA) circuitry, a direct current (DC)-DC converter, transceiver circuitry, and front-end aggregation circuitry. Embodiments of the RF communications system may relate to reducing cost, reducing size, reducing complexity, increasing efficiency, increasing performance, the like, or any combination thereof. | ||||||
| 184 | SYSTEM AND METHOD FOR POWER AMPLIFIER CONTROL SATURATION DETECTION AND CORRECTION | PCT/US2011027186 | 2011-03-04 | WO2011109708A2 | 2011-09-09 | RIPLEY DAVID S; ANDRYS PAUL R; BANOWETZ MATTHEW L |
| A system for power amplifier control saturation detection and correction includes a comparator configured to receive a power control signal and a detected power signal and generate a regulated voltage, a power amplifier configured to receive the regulated voltage and develop an output power, a power detector configured to sense the output power and develop the detected power signal, a saturation detector configured to receive the regulated voltage and a system voltage and determine whether the power amplifier is operating in a saturation mode during a transmit burst, and a current generator configured to reduce the power control signal when the power control signal exceeds a predetermined value and after expiration of a predetermined period of time, preventing the power control signal from exceeding the detected power signal. | ||||||
| 185 | ACCURATE BIAS TRACKING FOR PROCESS VARIATION AND SUPPLY MODULATION | PCT/IB2011003331 | 2011-12-20 | WO2012085685A8 | 2013-06-27 | LEONG POH BOON; MANIAM NUNTHA KUMAR KRISHNASAMY |
| A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled. | ||||||
| 186 | ACCURATE BIAS TRACKING FOR PROCESS VARIATION AND SUPPLY MODULATION | PCT/IB2011003331 | 2011-12-20 | WO2012085685A3 | 2013-05-10 | LEONG POH BOON; MANIAM NUNTHA KUMAR KRISNASAMY |
| A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled. | ||||||
| 187 | APPARATUS AND METHODS FOR ENVELOPE TRACKING | PCT/US2012034820 | 2012-04-24 | WO2012148918A2 | 2012-11-01 | BALTEANU FLORINEL G; KHESBAK SABAH; TKACHENKO YEVGENIY A; THOMPSON ROBERT JOHN; RIPLEY DAVID STEVEN |
| Apparatus and methods for envelope tracking are disclosed. In one embodiment, a power amplifier system including a power amplifier (32) and an envelope tracker (30) is provided. The power amplifier is configured to amplify a radio frequency (RF) signal, and the envelope tracker is configured to control a supply voltage of the power amplifier using an envelope of the RF signal. The envelope tracker includes a buck converter (73) for generating a buck voltage from a battery voltage and a digital-to-analog conversion (DAC) module (78, 79) for adjusting the buck voltage based on the envelope of the RF signal to generate the supply voltage for the power amplifier. | ||||||
| 188 | LOW NOISE AMPLIFIER AND MIXER | PCT/IB2010001132 | 2010-05-17 | WO2010136862A8 | 2011-03-03 | AMRUTUR BHARADWAJ; SANKARAGOMATHI KANNAN ARYAPERUMAL |
| A low noise amplifier (LNA) system with controllable linearity and noise figure versus power consumption is provided. The system comprises two control inputs for tuning. One input controls an effective transistor width, and the other input controls bias current. Changes to the effective transistor width alter a gain that is applied to a signal, and changes to the bias current alter a power consumption of the system. For more stringent signal specifications, an impedance matched inductive degeneration variation of the LNA is provided. | ||||||
| 189 | CHAÎNE DE RÉCEPTION DE SIGNAUX ELECTROMAGNÉTIQUES IMPULSIONNELS | EP15808645.4 | 2015-12-15 | EP3235124B1 | 2018-10-10 | GARREC, Patrick; PLAZE, Jean-Philippe; MALLET-GUY, Benoît |
| 190 | OPERATIONAL AMPLIFIER BASED CIRCUIT WITH COMPENSATION CIRCUIT BLOCK USED FOR STABILITY COMPENSATION | EP15191878.6 | 2015-10-28 | EP3021482B1 | 2018-09-19 | Yu, Chi-Yao |
| An operational amplifier based circuit (100) has an operational amplifier (102), a feedback circuit (104), and a compensation circuit block (106). The feedback circuit (104) is coupled between an output port and an input port of the operational amplifier (102). The compensation circuit block (106) has circuits involved in stability compensation of the operational amplifier (102), wherein there is no stability compensation circuit driven at the output port of the operational amplifier (102). | ||||||
| 191 | Pseudo-envelope following power management system | EP14162682.0 | 2011-04-19 | EP2782247B1 | 2018-08-15 | Khlat, Nadim; Kay, Michael, R. |
| Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system used to manage the power delivered to a linear RF power amplifier. | ||||||
| 192 | MULTI-STAGE AMPLIFIER WITH CASCODE STAGE AND DC BIAS REGULATOR | EP16774732.8 | 2016-08-05 | EP3335313A1 | 2018-06-20 | KAPER, Valery, S. |
| A multi-stage amplifier having a first amplifier stage comprising: a pair of transistors arranged in a cascade amplifier arrangement; and an isolation circuit; and a second amplifier stage coupled to an output of the first amplifier stage; and bias regulator having a reference transistor. The cascode amplifier stage includes a pair of transistors arranged in a cascode amplifier arrangement. The bias regulator produces a reference current through the reference transistor and DC bias voltages for the control electrodes of each of the pair of transistors in the cascode amplifier arrangement and for the second stage's transistor as a function of the reference current through the reference transistor. | ||||||
| 193 | BIASED TRANSISTOR MODULE | EP16177378.3 | 2016-06-30 | EP3264596A1 | 2018-01-03 | Bergervoet, Jozef Reinerus Maria; de Jong, Gerben Willem; Hoogzaad, Gian |
A biased-transistor-module comprising: a module-input-terminal; a module-output-terminal; a reference-terminal; a module-supply-terminal configured to receive a supply voltage; a module-reference-voltage-terminal configured to receive a module reference voltage; a main-transistor having a main-control-terminal, a main-first-conduction-channel-terminal and a main-second-conduction-channel-terminal, wherein the main-first-conduction-channel-terminal is connected to the module-output-terminal, and the main-second-conduction-channel-terminal is connected to the reference-terminal, and the main-control-terminal is connected to an input-signal-node, wherein the input-signal-node is connected to the module-input-terminal; and a bias-circuit. The bias-circuit comprises: a first-bias-transistor; a first-bias-resistor; a second-bias-transistor; and a second-bias-resistor.
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| 194 | A METHOD AND APPARATUS FOR ENVELOPE TRACKING | EP14867856.8 | 2014-12-02 | EP3036830B1 | 2017-11-08 | MIDYA, Pallab; AI-QAQ, Wael; JIANG, Hong |
| 195 | DIFFERENTIAL AMPLIFIERS | EP15813514.5 | 2015-12-14 | EP3235126A1 | 2017-10-25 | CORBISHLEY, Phil |
| Stabilization of the common-mode output voltage of a differential amplifier by use of a replica circuit The common-mode output voltage of differential pair amplifier 2 is controlled by use of a replica circuit 4 with a control loop acting on the current sources 32 and 10. The amplifier 28 in the control loop adjusts the gate voltage applied to the current source transistor 32 so that the voltage at the drain of the replica transistor 30 equals the reference voltage 36. The common mode output voltage of the working amplifier 2 may thus be controlled without feedback from the output of the this amplifier, thereby avoiding stability problems and reducing power consumption. The components in the dummy circuit 4 are scaled with respect to the components in the amplifier 2 so that the dummy circuit 4 consumes little current. | ||||||
| 196 | PROCÉDÉ DE GESTION ÉNERGÉTIQUE D'UN AMPLIFICATEUR FAIBLE BRUIT DANS UNE CHAINE DE RÉCEPTION DE SIGNAUX ÉLECTROMAGNÉTIQUES, ET CHAINE DE RÉCEPTION METTANT EN OEUVRE UN TEL PROCÉDE | EP15808645.4 | 2015-12-15 | EP3235124A1 | 2017-10-25 | GARREC, Patrick; PLAZE, Jean-Philippe; MALLET-GUY, Benoît |
| The present invention relates to a method for managing the power use of electronic components in a channel for receiving electromagnetic pulse signals. Said invention also relates to a receiving channel implementing such a method. The invention is particularly of use for low-noise amplifiers and for the various electronic receiving units of radar listening systems. The low-noise amplifier (10) operates with a power supply voltage and a polarization current. Said power supply voltage and/or said current are controlled based on the amplitude of each received signal. Control (1, 2) is carried out based on the measurement of said amplitude. | ||||||
| 197 | CLOCK AND DATA DRIVERS WITH ENHANCED TRANSCONDUCTANCE AND SUPPRESSED OUTPUT COMMON-MODE | EP14859633 | 2014-11-05 | EP3066756A4 | 2017-07-12 | SU WENJUN; YIN GUANGMING; ZHU QUANQING |
| 198 | MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING | EP14857354 | 2014-11-04 | EP3066753A4 | 2017-06-21 | SIGNOFF DAVID M; HE MING; LOEB WAYNE A |
| A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. | ||||||
| 199 | AMPLIFIER ARRANGEMENT AND SWITCHED CAPACITOR INTEGRATOR | EP15198050.5 | 2015-12-04 | EP3176945A1 | 2017-06-07 | Steiner, Matthias; Fitzi, Andreas |
An amplifier arrangement has a first differential stage with a first transistor pair, a second differential stage with a first and a second transistor pair, each pair having a common source connection coupled to a drain terminal to a respective one of the transistors of the first differential stage. The amplifier arrangement further has a first complementary differential stage with a transistor pair having opposite conductivity type compared to the transistor pair of the first differential stage, and a second complementary differential stage with a first and a second transistor pair of the complementary conductivity type. The first and the second complementary differential stage are connected symmetrically compared to the first and the second differential stage. The transistors of the second complementary differential stage are symmetrically connected to the transistors of the second differential stage such that respective first, second, third and fourth current paths are formed. A pair of output terminals is coupled to the first and the second current path. Gate terminals of the transistors of each of the stages are coupled to a respective pair of input terminals.
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| 200 | HIGH BANDWIDTH POWER SUPPLY SYSTEM WITH HIGH EFFICIENCY AND LOW DISTORTION | EP10802603 | 2010-06-18 | EP2457133A4 | 2017-05-17 | JENSEN BRENT ROGER; DROGI SERGE FRANCOIS; TOMASZ MARTIN |
| A power supply system uses improved Class G amplifier architecture for high bandwidth operation with low distortion. The power supply system switches between multiple power supply rails, depending on the signal level handled by the power supply system. The lowest usable supply rail voltage is chosen to minimize power dissipation in the output driver, thus optimizing efficiency. Each supply rail has an associated driver capable of sourcing current to the amplifier output. When a supply rail is selected, its associated driver is enabled and other driver(s) not associated with the selected supply rail are disabled via separate disable control signals. The disabling of the deselected driver may be delayed until current above a predetermined threshold is sensed at the output of the enabled driver. In addition, the frequency of switching between the power rails may be limited via various means designed to limit distortion in the power supply system. | ||||||
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