Disclosed is an amplifier circuit with cross wiring of direct-current signals and microwave signals. The circuit includes a circuit network unit formed of a direct-current feeding circuit and a microwave power signal circuit. The direct-current feeding circuit starts from a high-electron-mobility transistor (HEMT) drain power-up bonding point (211), and is connected to a feeding end of a tail-level HEMT transistor core (250) via a corresponding line after being connected to a first Metal-Insulator-Metal (MIM) capacitor (221) in parallel, and connected to a first micro-strip inductor (222) and symmetrical branch micro-strips (223) in series, the branch micro-strips (223) being connected to one of electrodes of second MIM capacitors (231, 234) in series. The microwave power signal circuit starts from a signal end of the tail-level HEMT transistor core (250), is combined into two paths by a corresponding line, the two paths being respectively connected to two third MIM capacitors (241, 242) in parallel, being respectively connected to the other electrode of the second MIM capacitors (231, 234) in series, being respectively connected to ground micro-strip inductors (232, 235) in parallel and respectively connected to second micro-strip inductors (233, 236) in series, and being combined into one path to be connected to a third micro-strip inductor (238), and is output by a fourth MIM capacitor (239) connected in parallel. This solution reduces the tuning allowance of a matching network, improves the output impedance of a combined port, improves a chip space utilization rate, improves heat dissipation performance, and improves power density.

To provide an adder capable of obtaining an addition signal of a plurality of high frequency signals, and also a power combiner, a quadrature modulator, a quadrature demodulator, a power amplifier, a transmitter, and a wireless communicator, each of which uses the adder. Impedances (Zg, Zh) seen from a common output point (P3) of a plurality of first impedance circuits (110a, 110b) toward respective input terminals (102a, 102b) are set so that high frequency currents (Ig, Ih) are approximately zero. An impedance (Zs) seen from a first connection point (P1) toward the input terminals (102a, 102b) is set so that a high frequency current (Is) is approximately zero. An impedance (Zc) seen from the first connection point (P1) toward a circuit (150) is set so that a high frequency current (Ic) is approximately zero. An impedance (Zm) seen from a second connection point (P2) toward a power supply is set so that a high frequency current (Im) is approximately zero.

A switch apparatus of the invention comprises a first input terminal, a second input terminal to which a second input signal having a level lower than a level of the first input signal is supplied, a first switch block for outputting the first input signal supplied from the first input terminal through a plurality of switching elements, a second switch block for outputting the second input signal supplied from the second input terminal through a plurality of switching elements; and a control terminal to which a control signal is supplied wherein the control signal controls the first switch block when outputting the first input signal, and controls the second switch block when outputting the second input signal, wherein the first switch block is configured to have a smaller number of switching elements than that of the second switch block.

An RF amplification device comprises amplification elements Q11 and Q12 which amplify a radio frequency input signal Pin_LB in wireless radio communication, and transmission line transformers TLT11, TLT12, coupled to one of an input electrode and an output electrode of the amplification element. The TLT11, TLT12 comprise a main line Lout arranged between the input and the output, and a sub line Lin1 arranged between an AC ground point and one of the input and the output and coupled to the main line Lout. By applying an operating voltage Vdd different from the ground voltage level GND to the AC ground point, the operating voltage Vdd is supplied to the output electrodes of the amplification elements Q11, Q12 via the sub line Lin from the AC ground point. In realizing a high-performance load circuit in an RF amplification device, it is possible to avoid increase of a module height of an RF module, and at the same time, to avoid increase of an occupied area of a load circuit of a high-frequency amplifier which is formed over a semiconductor chip or a multilayer wiring circuit substrate.

An amplification apparatus includes an amplifier (202, 204, 205). The amplification apparatus includes a bias voltage circuitry (208) coupled to the amplifier (202, 204, 205) to provide a bias voltage thereto. The amplification apparatus includes a supply voltage circuitry (207) coupled to the amplifier (202, 204, 205) to provide a supply voltage thereto. The supply voltage circuitry (207) is coupled to the bias voltage circuitry (208). The bias voltage circuitry (208) is configured to provide the bias voltage depending on the supply voltage.

An amplification apparatus includes an amplifier (202, 204, 205). The amplification apparatus includes a bias voltage circuitry (208) coupled to the amplifier (202, 204, 205) to provide a bias voltage thereto. The amplification apparatus includes a supply voltage circuitry (207) coupled to the amplifier (202, 204, 205) to provide a supply voltage thereto. The supply voltage circuitry (207) is coupled to the bias voltage circuitry (208). The bias voltage circuitry (208) is configured to provide the bias voltage depending on the supply voltage.

In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is placed at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is. Particularly, in a high-frequency power amplifier module provided with a semiconductor chip having multistage amplifying transistors on a wiring substrate: an angle formed by a first auxiliary line connecting bonding portions to each other at the two ends of an input bonding wire connecting a bonding input electrode for a specific one of the amplifying transistors to the wiring substrate and a second auxiliary line connecting bonding portions to each other at the two ends of an output bonding wire connecting an bonding output electrode for another amplifying transistor at a stage following the specific amplifying transistor to the wiring substrate is in the range 72 degrees to 180 degrees; and a gap between bonding portions of the bonding input electrode and the bonding output electrode is at least 0.3 mm but smaller than 0.8 mm. As a result, the high-frequency characteristic of the power amplifier module can be improved and the size thereof can be reduced.

An inter-stage matching circuit 26 comprises a one-stage high pass filter type matching unit 28 and a one-stage low pass filter type matching unit 29 serially connected with each other.

An integrated circuit for a transceiver comprises: a power amplifier, PA, output stage (120) comprising a first transistor (122) and a second transistor (124); a low noise amplifier, LNA, input stage (126) comprising a third transistor (128) and a fourth transistor (130); a differential impedance matching circuitry (108) configured to be connected to an antenna (102), wherein the differential impedance matching circuitry (108) comprises a first node (112) on one side and a second node (114) on an opposite side, wherein the first and third transistors (122; 128) are connected to the first node (112) and the second and fourth transistors (124; 130) are connected to the second node (114); wherein the differential impedance matching circuitry (108) comprises a third node (116) arranged between the first and second nodes (112; 114) and arranged to selectively receive a first or a second voltage.

According to an embodiment, a power amplifier includes: an MMIC substrate; a high frequency probe pad disposed on the MMIC substrate; and a metal plate disposed on the MMIC substrate so as to adjoin to the high frequency probe pad, and connected to an MMIC external circuit via a bonding wire.