| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Power amplifier | JP2011093210 | 2011-04-19 | JP5361934B2 | 2013-12-04 | 春揚 黄; 一考 高木 |
| 142 | Power amplifier | JP2011093210 | 2011-04-19 | JP2012227342A | 2012-11-15 | NG CHOON YONG; TAKAGI KAZUTAKA |
| PROBLEM TO BE SOLVED: To provide a power amplifier which is space-saving and reduces the effect of a bonding wire connecting an MMIC and an external circuit of the MMIC in a relatively simple configuration.SOLUTION: There is provided a power amplifier comprising: an MMIC substrate; a high-frequency probe pad arranged on the MMIC substrate; and a metal plate arranged adjacent to the high-frequency probe pad on the MMIC substrate and used for connecting the MMIC to an external circuit of the MMIC with a bonding wire. | ||||||
| 143 | High frequency power amplification device | JP2011052994 | 2011-03-10 | JP2012191426A | 2012-10-04 | KONO TAKAYUKI; SEKI KENTA; SAKURAI SATOSHI |
| PROBLEM TO BE SOLVED: To provide a high frequency power amplification device that can reduce a talk current or reduce a phase deviation in output.SOLUTION: The high frequency power amplification device includes, for example, a plurality of power amplifying transistors Q1-Q5 different in transistor size and a plurality of impedance matching circuits IMN14, IMN2i, IMN3i, IMN5i, IMN2o, IMN3o, IMN5o, IMNo, and switches a signal path to be used according to a power command signal Vrmp. A Q1→Q2 path is used for high power, a Q1→Q3 path is used for intermediate power and a Q4→Q5 path is used for low power. The high frequency power amplification device is so configured that each signal path follows the same number of power amplifying transistor stages and the same number of impedance matching circuits. | ||||||
| 144 | Power amplifier | JP2010283156 | 2010-12-20 | JP2012134627A | 2012-07-12 | YAMAMOTO KAZUYA; MIYASHITA MIYO; MATSUZUKA TAKAYUKI; MUKAI KENJI |
| PROBLEM TO BE SOLVED: To provide a power amplifier with an interstage attenuator which can implement gain switching while suppressing a deterioration in input reflection loss before and after the gain switching, and can implement gain switching while suppressing an increase in phase shift difference before and after the gain switching.SOLUTION: IN, OUT are RF input/output terminals; and Tr1, Tr2 are HBTs (heterojunction bipolar transistors). Fa1, Fa2 are FETs (field effect transistors). Cc1, Cc2 are decoupling capacities; Vc1, Vc2 are collector power terminals of the power stages Tr1, Tr2; Ra1, Ra2, Raa2, Rg1, Rg2 are resistance; Cs1 is an interstage matching capacity; Cp1 is an attenuator parallel capacity; and Vg1, Vg2 are attenuator control terminals. A capacity Ca1 is disposed in series with the resistance Ra1. | ||||||
| 145 | Rf power amplifier and operation method thereof | JP2010130163 | 2010-06-07 | JP2011259083A | 2011-12-22 | MORIMOTO TAKAAKI; KURIYAMA SATORU; TANAKA SATOSHI; NAKAMURA HAYATO |
| PROBLEM TO BE SOLVED: To reduce increase in a mounting area due to a DC voltage converter by reducing current consumption during low power output.SOLUTION: An RF power amplifier 200 comprises: a driver stage amplifier 230 which operates with external power supply voltages Vcc1, 2, and 3; a first RF amplifier 270a; a second RF amplifier 270b; and a DC voltage converter 280. Output from the driver stage amplifier 230 is supplied to the inputs of the first and second RF amplifier 270a and 270b, and the mounting element size of the first RF amplifier 270a is set larger than that of the second RF amplifier 270b. The external power supply voltage Vcc3 is supplied to the DC voltage converter 280, and the DC voltage converter 280 generates an operation power supply voltage Vcc4 of low voltage and supplies the operation power supply voltage Vcc4 to the output terminal of the second RF amplifier 270b. The external power supply voltage Vcc2 can be supplied to the output terminal of the first RF amplifier 270a not through the DC voltage converter 280. | ||||||
| 146 | High frequency power amplifier and operating method thereof | JP2010041615 | 2010-02-26 | JP2011182018A | 2011-09-15 | OTA IKUMA; HAYASHI NORIO; TSUTSUI TAKAYUKI; MORISAWA FUMIMASA; HASE MASATOSHI |
| <P>PROBLEM TO BE SOLVED: To reduce a variation of power gain resulting from the dependence on gate length of a power amplification field effect transistor. <P>SOLUTION: The high-frequency power amplifier comprises, over a semiconductor chip, a bias control circuit 112, a bias transistor 516 and an amplification transistor 513 which are coupled so as to configure a current mirror circuit, and a gate length monitor circuit 101 comprising a replicating transistor 421. The amplification transistor 513 amplifies an RF signal and a bias current of the bias control circuit 112 is supplied to the bias transistor 516. The transistor 516, 513 and 421 are fabricated by a same semiconductor manufacturing process, and have a same variation of gate length. The gate length monitor circuit 101 generates a detection voltage Vmon depending on the gate length L. According to the detection voltage, the bias control circuit 112 controls the bias current, thereby compensating the gate length dependence of transconductance of the amplification transistor 513. <P>COPYRIGHT: (C)2011,JPO&INPIT | ||||||
| 147 | ＲＦ増幅装置 | JP2008556018 | 2007-12-19 | JPWO2008093477A1 | 2010-05-20 | 大西 正己; 正己 大西; 田中 聡; 聡 田中; 亮一 田中 |
| 無線通信の無線周波数入力信号Pin_LBを増幅する増幅素子Q11、Q12と、増幅素子の入力電極と出力電極との一方に接続された伝送線路変圧器TLT11、12とを含む。TLT11、12は、入力と出力との間に配置された主線路Loutと、入力と出力とのいずれか一方と交流接地点との間に配置され主線路Loutと結合された副線路Linとを含む。交流接地点に接地電圧レベルGNDと異なる動作電圧Vddが印加されることにより、交流接地点から副線路Linを介して増幅素子Q11、Q12の出力電極に動作電圧Vddが供給される。RF増幅装置において高性能の負荷回路を実現する際にRFモジュールのモジュール高さの増大を回避するとともに半導体チップもしくは多層配線回路基板で構成される高周波増幅器の負荷回路の占有面積の増大を回避することができる。 | ||||||
| 148 | Adder, power combiner, orthogonal modulator, orthogonal demodulator, power amplifier, transmitter and radio communication equipment using the adder | JP2008284912 | 2008-11-05 | JP2010113483A | 2010-05-20 | NAGAYAMA AKIRA; FUKUOKA YASUHIKO |
| <P>PROBLEM TO BE SOLVED: To provide an adder obtaining the addition signal of a plurality of high frequency signals and a power combiner, an orthogonal modulator, an orthogonal demodulator, a power amplifier, a transmitter and radio communication equipment each using the adder. <P>SOLUTION: Impedances (Zg, Zh), when input terminals (102a, 102b) side of a plurality of first impedance circuits (110a, 110b) are viewed from a common output point (P3) of the first impedance circuits (110a, 110b), are set so that high frequency currents (Ig, Ih) can be set to almost zero. Impedance (Is), when the input terminals (102a, 102b) side are viewed from a first connection point (P1) is set so that a high frequency current (Is), can be set to almost zero. Impedance (Zc), when a circuit (150) side is viewed from the first connection point (P1), is set so that a high frequency current (Ic) can be set to almost zero. Impedance (Zm), when a power source side is viewed from a second connection point (P2) is set so that a high frequency current (Im) can be set to almost zero. <P>COPYRIGHT: (C)2010,JPO&INPIT | ||||||
| 149 | 高周波増幅器 | JP2008548105 | 2006-11-30 | JPWO2008068809A1 | 2010-03-11 | 森 一富; 一富 森; 和宏 弥政; 太田 彰; 彰 太田; 紫村 輝之; 輝之 紫村; 正敏 中山 |
| 素子サイズの異なる2つの増幅素子を並列に接続し、出力電力の大小に応じて増幅素子を切替える高周波増幅器であって、特に、出力電力が大きい場合と小さい場合のいずれの場合でも、特性インピーダンス(50オーム)に整合するとともに、2つの増幅素子の出力側の接続点からOFFしている増幅素子を見たインピーダンスを高くする出力整合回路を設けた。その結果、高出力、高効率の特性を実現することができ、また、増幅された高周波信号がOFFしている増幅素子側の整合回路に回りこむことを抑えることができるという効果を奏する。 | ||||||
| 150 | 高出力増幅器 | JP2006527672 | 2004-07-14 | JPWO2006006244A1 | 2008-04-24 | 森 一富; 一富 森; 新庄 真太郎; 真太郎 新庄; 公春 服部; 高橋 利成; 利成 高橋; 博昭 関; 太田 彰; 彰 太田; 末松 憲治; 憲治 末松 |
| 増幅素子3の出力電力に応じて、最終段の増幅素子3と出力端子8間に接続されている出力整合回路5の整合条件を変更する。これにより、最大出力時の効率を低減することなく、低出力時の効率を大幅に高めることができる。また、DC−DCコンバータを搭載する必要がないので、大型化やコスト高の発生を防止することができる。 | ||||||
| 151 | Power amplifier module | JP2000101205 | 2000-03-31 | JP2001284984A | 2001-10-12 | MATSUMOTO HIDETOSHI; TAGAMI TOMONORI; TANAKA SATOSHI; YAMASHITA KIICHI |
| PROBLEM TO BE SOLVED: To provide a power amplifier module which is easily integrated at a low-cost and has high efficiency and high linearity. SOLUTION: For each step of the power amplifier module composed of plural amplifiers, a reference amplifier is provided for simulating the operation of the amplifier and a current to flow to the base of a bipolar transistor to become the core of this reference amplifier corresponding to an input power level is detected, amplified and supplied as the base current of the transistor to become the core of the amplifier. Thus, the power amplifier module of high efficiency and low distortion can be provided with high reproducibility. COPYRIGHT: (C)2001,JPO | ||||||
| 152 | 一种功放装置及用户设备的接收装置 | CN200920177821.7 | 2009-08-31 | CN201528316U | 2010-07-14 | 汪海 |
| 本实用新型涉及一种功放装置及用户设备的接收装置，其中，功放装置包括：第一级功放管，增益放大所有的输入信号；与所述第一级功放管连接的第一级偏置电路，向所述第一级功放管提供偏置电压；与所述第一级功放管连接的第二级功放管，增益放大所述第一级功放管的输出信号；与所述第二级功放管连接的第二级偏置电路，向所述第二级功放管提供偏置电压；与所述第一级偏置电路、第二级偏置电路连接的参考电压单元；与所述第一级偏置电路、第二级偏置电路连接的控制电压单元，通过所述第一级偏置电路和第二级偏置电路分别控制所述第一级功放管和第二级功放管的导通与关断。通过简化功放装置的结构，降低了生产成本，提高了增益过程的稳定性。 | ||||||
| 153 | APPARATUS AND METHODS FOR CAPACITIVE LOAD REDUCTION | PCT/US2011063821 | 2011-12-07 | WO2012078808A3 | 2012-10-04 | KACZMAN DANIEL LEE; YOUNG JAMES PHILLIP |
| Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes an envelope tracker configured to provide a supply voltage to a plurality of power amplifiers. The power amplifiers include power supply inputs electrically connected in a star configuration so as to reduce a capacitive load of the envelope tracker. The distributed capacitance of the power amplifiers is used to provide RF grounding so as to reduce the size of or eliminated the use of bypass capacitors. | ||||||
| 154 | SYSTEM AND METHOD FOR BIASING A POWER AMPLIFIER | PCT/US2011046971 | 2011-08-08 | WO2012021461A3 | 2012-06-28 | GREEN DUANE A; SHU WEIWEI; SAWATZKY DAVID |
| A system and method for biasing a power amplifier includes a power amplifier having a driver stage and an output stage, the driver stage having a plurality of driver devices, a bias current source configured to deliver a bias current to each of the plurality of driver devices, and a current directing element configured to receive the bias current and selectively bias each of the plurality of driver devices based on a reference voltage and a system voltage. | ||||||
| 155 | RF POWER AMPLIFIERS WITH LINEARIZATION | PCT/US2009045354 | 2009-05-27 | WO2009155010A3 | 2010-03-11 | ALIDIO RAUL; DUPUY ALEXANDRE; GUMMALLA AJAY; LEE WOO YONG; ACHOUR MAHA |
| Designs and techniques associated with power amplifiers for amplifying RF signals to provide variable power amplification and improved linearity in various RF amplification circuits, including power amplifiers operated under the power back-off conditions. | ||||||
| 156 | BIAS-MANAGEMENT SYSTEM AND METHOD FOR PROGRAMMABLE RF POWER AMPLIFIER | PCT/US0341637 | 2003-12-22 | WO2004059832A3 | 2005-03-31 | HEDBERG DAVID J; TURNER JAMES B |
| A system (100) and method (200) for adaptively managing bias of an RF power amplifier (102) is provided. The system (100) incorporates a controller (116) configured to select a radio operating mode. A current-mirror circuit (114) is coupled to the controller (116) and configured to produce a reference current (IRef) as a function of the radio operating mode. A bias regulator (104) is coupled to the controller (116) and the current-mirror circuit (114) and configured to produce a driver-stage bias current (Ib1) and an output-stage bias current (Ib2) for the power amplifier (102) in response to the reference current (IRef). The system (100) also incorporates a DC-to-DC converter (118) coupled to the controller (116) and configured to provide a supply voltage (Vcc) for the power amplifier (102) in response to the radio operating mode. The system (100) also incorporates an envelope detector (120) configured to produce an envelope current (IEnv) in response to an RF input signal (126). The system (100) causes the reference current (IRef) to vary as a function of the envelope current (IEnv). | ||||||
| 157 | 増幅器 | JP2016116301 | 2016-06-10 | JP2017220893A | 2017-12-14 | 若木 謙; 渡邊 大介 |
| 【課題】増幅器の利得を所望の値に近づくように制御する。 【解決手段】本発明の一実施形態による増幅器1は、接地点SGと電源Vddとの間に接続された第1トランジスタFET1および第2トランジスタFET2を備える。第1トランジスタFET1の制御端子Gは、入力端子Pinに接続されている。第1トランジスタFET1の第1端子Sは、接地点SGに接続されている。第2トランジスタFET2の第2端子Dは、出力端子Poutに接続されている。増幅器1は、インピーダンス要素L10と、可変抵抗部Rv11とをさらに備える。インピーダンス要素L10は、第2トランジスタFET2の第2端子Dおよび電源Vddの間に接続されている。可変抵抗部Rv11は、第1トランジスタFET1の第2端子Dおよび第2トランジスタFET2の第1端子Sの間に接続されている。 【選択図】図2 |
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| 158 | 電力増幅回路 | JP2016064501 | 2016-03-28 | JP2017183839A | 2017-10-05 | 長谷 昌俊 |
| 【課題】回路面積の増大を抑制しつつ、大信号入力時にも適用可能なスイッチ回路を備える電力増幅回路を提供する。 【解決手段】電力増幅回路は、第1の無線周波数信号が供給されるエミッタと、第1のDC制御電流又はDC制御電圧が供給されるベースと、第1の無線周波数信号に応じた第1の出力信号を出力するコレクタと、を有する第1のトランジスタと、第1の出力信号を増幅し、第1の増幅信号を出力する第1の増幅器と、第1の出力信号の出力を制御するために、第1のトランジスタのベースに第1のDC制御電流又はDC制御電圧を供給する第1の制御回路と、を備える。 【選択図】図1 |
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| 159 | 電力増幅回路 | JP2016023057 | 2016-02-09 | JP2017143388A | 2017-08-17 | 長谷 昌俊 |
| 【課題】中間電力出力時の利得伸長を抑制しつつ消費電流を低減する。 【解決手段】電力増幅回路は、第1の信号が入力され第1の信号を増幅した第2の信号を出力する第1の増幅器と、第1の増幅器にバイアス電流又はバイアス電圧を供給するバイアス回路と、第1の信号の信号レベルに応じた制御電圧を生成する制御電圧生成回路と、を備え、バイアス回路は、バイアス電流又はバイアス電圧を出力する第1のトランジスタと、第1のトランジスタのエミッタ又はソースと接地との間に設けられた第2のトランジスタと、ベース又はゲートに制御電圧が供給されエミッタ又はソースから第2のトランジスタのベース又はゲートに第1の電流又は電圧を供給する第3のトランジスタと、を備え、信号レベルが第1のレベルの場合における第1の電流又は電圧の値は、信号レベルが第2のレベルの場合における第1の電流又は電圧の値より大きく、第1のレベルは第2のレベルより高い。 【選択図】図3 |
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| 160 | バンプ付き電子部品及びバンプ付き電子部品の製造方法 | JP2013211181 | 2013-10-08 | JP6143104B2 | 2017-06-07 | 大部 功; 長壁 伸也 |
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