An electric power system simulator comprising first calculator which calculates a generator dynamic characteristic, second calculator which calculates a load dynamic characteristic and third calculator which calculates power transmission condition of an electric power system network, then the first calculator cyclically obtains an amplitude and a phase of an internal induced voltage of the generator based on data on an output power and a terminal voltage of the generator, and the second calculator calculates a load equivalent admittance at predetermined time based on data on an A.C. voltage at a load installation point, and the third calculator calculates a current flowing in each element of the electric power system based on respective data obtained by the first calculator and the second calculator and an electric power system network impedance to obtain the output power and terminal voltage of the generator, so that a condition change of the electric power system including the generators is serially simulated by alternately executing the calculations of the first and the second calculators and the calculation of the third calculator.

Zur getrennten Prüfung der analogen Schaltkreise und der digitalen Schaltkreise werden in die Leitungen, die die analogen und digitalen Schaltkreise miteinander verbinden, Trennzellen (TZ) eingefügt, durch die diese Leitungen (VL1, VL2) unterbrechbar sind. Die Zufuhr der Testsignale zu den digitalen Schaltkreisen (DBL) bzw. zu den analogen Schalt­kreisen (ABL) kann ebenfalls über die Trennzellen (TZ) er­folgen. Dazu können die Trennzellen (TZ) zu einem Schiebere­gister zusammengeschaltet werden, dem über äußere Anschlüsse (PIN) Testsignale zugeführt werden bzw. von dem von den Schaltkreisen abgegebene Testsignale zu einem äußeren Anschluß (PN) übertragen werden. Weiterhin ist es möglich, daß die Trennzellen (TZ) unabhängig voneinander im Parallelbetrieb arbeiten und dabei in den Trennzellen gespeicherte Testsignale den Schaltkreisen (ABL, DBL) zuführen bzw. im parallelen Betrieb von diesen Schaltkreisen ab gegebene Testsignale übernehmen. Trennzellen, die mit den analogen Schaltkreisen (ABL) verbunden sind, weisen eine Ausgangsstufe auf, die sicherstellt, daß an den Eingängen der analogen Schaltkreise im Schiebebetrieb keine Änderungen auftreten. Weiterhin ist es möglich, den analogen Schaltkreisen (ABL) im Testbetrieb die Testsignale parallel von äußeren Anschlüssen (PIN), die im Normalbetrieb mit den digitalen Schaltkreisen (DBL) verbunden sind, direkt zuzuführen. Dazu können Testmultiplexer (TMUX) vorgesehen sein. Die Aufteilung der Schaltkreise in einen digitalen Block (DBL) und einen analogen Block (ABL) ist deswegen zweckmäßig, da dann die Entwicklung der zu verwen­denden Prüfprogramme wesentlich erleichtert wird.

La présente invention concerne un convertisseur numérique/analogique pour convertir en une valeur analogique la somme pondérée de valeurs binaires (X, Y) comprenant : un ensemble de cellules identiques, chaque cellule correspondant à des bits de même rang de chaque valeur binaire, chaque cellule comprenant en­tre une source de tension haute (VCC) et une source de tension basse (M) une résistance série (20) dont la deuxième borne (21) est reliée à une pluralité de sources de courant commutables, cha­que source de courant ayant une valeur (I, J) correspondant à la pondération (A, B) de la valeur binaire (X, Y) correspondante, la résistance série de la cellule du bit le moins significatif ayant une valeur R, la résistance série de la cellule du bit le plus si­gnificatif ayant une valeur quelconque non nulle (R_L), la résis­tance série des autres cellules ayant une valeur 2R ; des résis­tances de valeurs R reliant entre elles lesdites deuxièmes bornes des diverses cellules ; et des moyens de sortie aux bornes de la­dite résistance série de la cellule du bit le plus significatif.

A maximum-likelihood sequence estimator receiver includes a matched filter (56) connected to a digital transmission channel (58) and a sampler (60) for providing sampled signals output by the matched filter (56). The sampled signals are input to an analog neural network (68) to provide high-speed outputs representative of the transmission channel signals. The neural network outputs (70) are also provided as inputs to a coefficient esitmator (78) which produces coefficients for feedback to the matched filter (56). For time-varying transmission channel characteristics, the coefficient estimator (78) provides a second coefficient output which is utilized for changing the interconnection strenghts of the neural network connection matrix to offset the varying transmission channel characteristics.

A high speed four quadrant multiplier is current controlled and uses a high speed differential output current digital to analog converter. Independent adjustment of the multiplying factor without changing the DC offset is accomplished. Also a true zero input signal will cause a true zero output signal and the operation of the multipler is extremely fast. The analog throughput of the multiplier is independent of the speed of the digital to analog converter.

A D'A converter comprising current-voltage converter means (22) which converts a constant current from a constant-current circuit into a voltage an integrating circuit (26), a switched capacitor (23) that is provided between said current-voltage converter means (22) and said integrating circuit (26) and controls the amount of electric charge supplied to said integrating circuit, and first and second control signal generating circuits (28, 31) respectively comprising counters (29, 32) and comparators (30, 33) which are served with first and second digital input signals to control the number of times of opening and closing the switched capacitor (23). An analog signal proportional to the product of said first and second digital input signals is produced from said integrated circuit (26). This enables the structure to be simplified and the cost to be reduced.

A digital representation of the time-integral of the illumination-dependent electric current flowing in a photo- conductive diode (1) is produced by feeding the current initially to the first (3a) of a series of capacitors (3a-3d). When the voltage across this first capacitor reaches a predetermined value the current is subsequently directed to the next capacitor (3b) of the series, and so on for the remaining capacitors in succession, by means of a coupling circuit (6). At the end of the integration period the voltage level in that capacitor which is only partly charged at that time is converted to digital form by means of a corresponding analog-to-digital converter (16) and applied to an output (18) together with a code identifying from which capacitor the digital output has been derived. If the number of capacitors and also the capacitance of each capacitor relative to that of the previous one is suitably chosen the arrangement can cope with a very large range of values of the integral of the input current. The capacitors (3) together with the coupling means (6) may be replaced by a charge-coupled device structure comprising a series of charge wells where each well can overflow into the next well of the series.

A circuit (10) for extracting the square root of an incoming voltage signal utilizes a four-bit up/down counter (14) to control the output duty cycle of a pair of four-bit rate multipliers (16, 18) connected in a cascaded configuration. The output of the second rate multiplier (18), which is related to the square of the up/down counter value, is used to control the mode of the counter (14) so as to track the incoming voltage signal. Inasmuch as the square of the up/down counter value is tracking the incoming voltage signal, the output duty cycle of the first rate multiplier (16) in the cascaded pair is the square root of the incoming voltage signal which is subsequently converted into analog form. The circuit also utilizes a "dithering" technique so that the resulting square root output signal has greater than four-bit accuracy.

A function generator for extracting the square root or other function of a pulse width modulated input signal utilizes a ROM table (12) which contains values of the inverse of the desired function. Two eight-bit counters (26, 28) are clocked in proportion to the duty cycle of the input signal and the duty cycle of a flip-flop (22), which is related to the output of the ROM table (12). The counters (26, 28) keep a running average of the comparison of the foregoing duty cycles and, in turn, cause a four-bit up/down counter (30) and the ROM (12) to cycle in time between the value in the ROM (12) above and below the exact input value. In this manner, the output of a four-bit up/down counter (30) is an accurate interpolated representation of the square root of the input signal.

In apparatus for processing an analog signal, a successive approximation ADC comprises a successive approximation register and a DAC. The final digital signal generated by the ADC is applied to digital processing equipment, such as a digital delay, and the output signal from the processing equipment is converted to analog form using the DAC of the ADC.

A high speed four quadrant multiplier is current controlled and uses a high speed differential output current digital to analog converter. Independent adjustment of the multiplying factor without changing the DC offset is accomplished. Also a true zero input signal will cause a true zero output signal and the operation of the multipler is extremely fast. The analog throughput of the multiplier is independent of the speed of the digital to analog converter.

The object of the present invention is to provide an improved convolution processor that requires no multiplication operations and can easily be implemented digitally.

The convolution processor comprises a first delta analog to digital converter (3) disposed in a first path (1) for one of first (f(t)) and second (g(t)) input waveforms being operated on to provide a convolution function to convert signals in the first path to a digital version thereof having a delta modulation format; a second delta analog to digital converter (4) disposed in a second path (2) for the other of the first and second input waveforms to convert signals in this second path to a digital version thereof having the delta modulation format; a summer (5) coupled to the output of the first and second paths and a pair of integrators (6, 7) coupled in any of the following manner in the above circuit; namely, in the first path, in the second path, in the first and second paths, in the output of the summer, in the first path and the output of the summer, and in the second path and the output of the summer. The convolution function is provieded at the output of the summer when the pair of integrators is coupled in the first path, the second path and in the first and second paths while the convolution function output is provided at the output of at least one of the pair of integrators when the pair of integrators is coupled in the output of the summer, in the first path and the output of the summer and, in the second path and the output of the summer.