| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 321 | Signal processor | JP33139188 | 1988-12-27 | JPH02174422A | 1990-07-05 | KATO HISAO; ADACHI YASUSHI |
| PURPOSE: To obtain an output without noise by revising a processing mode of a data processing unit when an output of a D/A converter is completely attenuated so as to bring an output of the D/A converter into a complete attenuation state while an output data of the data processing unit is unstable. CONSTITUTION: Suppose that an output data C of a data processing unit is unstable for a time between '0' and t7 at application of power. As soon as power is applied, a signal Z is supplied from a power application confirming circuit 50 11B, which starts counting in response to the signal Z and supplies a signal 12 to a current control signal generating circuit 12 when the count for times of 0-t7 is counted out. The circuit 12 supplies an attenuation release signal K to a switch 20 in response to the signal 12. The circuit 12 responds to the attenuation release signal K and is selected to the position of a prediction device 14 for the normal operation. Since an analog signal D is in the completely attenuated state for times 0-t7 after application of power till a data C is made stable in such a way, a noise caused by an unstable data C is not generated. COPYRIGHT: (C)1990,JPO&Japio | ||||||
| 322 | Square root digital-analog converter | JP20950989 | 1989-08-11 | JPH02159124A | 1990-06-19 | SUKOTSUTO BII DONARUDOSON |
| PURPOSE: To attain a comparatively inexpensive monotonous 24-bit digital-analog converter by using an 8-bit digital-analog converter and a simple mutual conductance amplifier as a multiplier in a feedback circuit of a square root amplifier. CONSTITUTION: An amplifier 26 forms a main forward amplifier of which inverted input is functioned as an additional node for input currents from amplifiers 22, 24 and a feedback current from an amplifier 44. An amplifier 42 is a mutual conductance amplifier having a full scale X input from a voltage divider including resistors 46, 48 and a full scale YX input from a current source amplifier 40, a transistor 49 and a resistor 50. When a digital input is ≤16 bits, switches 28, 70 are closed and all other switches are opened. The system acts as a 16-bit square root D/A converter followed by 1/16 attenuation. When the digital input exceeds 16 bits, the system acts as a 24-bit D/A converter. COPYRIGHT: (C)1990,JPO | ||||||
| 323 | JPH01177660U - | JP7416188 | 1988-06-02 | JPH01177660U | 1989-12-19 | |
| 324 | Sine wave oscillator | JP29592188 | 1988-11-22 | JPH01170105A | 1989-07-05 | BERUNERU MITSUTERUMAIERU; ERUBIN BIIBURU; TOOMASU MAUKUSHIYU |
| PURPOSE: To produce a sine wave signal with high accuracy by satisfying a specific expression for the frequency coefficient of a sine wave oscillator which carries out in sequence the multiplication and addition based on an addition theorem to produce a desired sine wave signal. CONSTITUTION: K=2.sin (π.f/P) is satisfied among sine value A (i+1)=A i+B i.K, cosine value B (i+1)=B i-A (i+1).K and frequency coefficient K respectively, where (f) and P show the set frequency and the clock frequency respectively. Then the value of the frequency (f) is inputted to a computer 1, and the coefficient K is calculated and stored in a memory 3. When the transmission controllers 6, 9, 12 and 13 are switched to (a), the output of a multiplexer 4 obtained by the coefficient K and the output of a latch 7 are inputted to an adder 5. Then the output of the adder 5 is inputted to the latch 7 and converted into new arithmetic value A (i+1). When the controllers 6 to 13 are switched to (b), the output A (i+1) of the latch 7 is inputted to the adder 5 via the multiplier 4 and subtracted from value B i of a latch 8. Then the output of the adder 5 is inputted to the latch 8 and converted into arithmetic value B (i+1). COPYRIGHT: (C)1989,JPO | ||||||
| 325 | Digital-to-analog converter | JP23619388 | 1988-09-20 | JPH01164124A | 1989-06-28 | SERUJIYU RAME |
| PURPOSE: To decrease the number of parts of an IC and to reduce the area of the IC by converting the binary weighted sum into the analog value. CONSTITUTION: The current sources 23A and 23B of every cell are placed in parallel to each other in number equal to digital words X and Y whose weighted sums are calculated. All sources 23A output the current I that is proportional to the value A to be multiplied by the value X, and all sources 23B output the current J that is proportional to the value B to be multiplied by the value Y. The switches 22A and 22B open or close according to the strings of bit value corresponding to value X and Y respectively. A resistance 20 has value 2R in all intermediate cells, value R in a cell 1 corresponding to the least significant bit and optional value RL except zero in a cell N corresponding to the most significant bit respectively. The analog value corresponding to a product (AX+BY) is shown at a terminal of resistance RL. Thus, the surface area of an IC can be reduced and a scalar produce can be easily obtained. COPYRIGHT: (C)1989,JPO | ||||||
| 326 | Converter | JP24470988 | 1988-09-30 | JPH01130625A | 1989-05-23 | MITSUSHIERU FUERII; KURISUCHIYAN JIYAGAARU |
| PURPOSE: To easily provide two transmission functions directly opposite to each other by performing an A/D conversion and a D/A conversion by the same constitution element. CONSTITUTION: The output of a digital-analog D/A converter 110 is connected to an attenuator 120 and the output of the attenuator 120 is connected to the input of a comparison mechanism 150 and a sample-and-hold S/H circuit 130. The output of the S/H circuit 130 supplies an analog amount reacting to digital output transmitted through a bus 115 to control logic 140 to a lead wire 185. Also, the output of the comparison mechanism 150 is sent to the control logic 140 and the control logic 140 controls the S/H circuit 160, the D/A converter 110, the attenuator 120 and the S/H circuit 130 and supplies the digital output corresponding to the analog amount inputted to the S/H circuit 160 to the bus 125. Thus, without using the members of high accuracy, the two transmission functions in completely opposite relation are easily realized. COPYRIGHT: (C)1989,JPO | ||||||
| 327 | Digital signal processing circuit | JP4172687 | 1987-02-25 | JPS63209209A | 1988-08-30 | IWAMATSU MASAYUKI |
| PURPOSE: To minimize the influence of the converting error of an A/D conversion and to prevent the deterioration of S/N providing a means to attenuate to an A/D converted digital signal to the value in which the digital signal processing means is not overflown at the input side of a digital signal processing means. CONSTITUTION: The analog signal of a processing object is converted to a digital signal with an A/D converter 10. The digital signal is inputted through a signal line 11 equivalent to a digital signal supplying means to an attenuator 18 equivalent to a digital signal attenuating means and attenuated in a prescribed quantity digital way. After a prescribed digital signal processing is executed by a digital signal processing part 12 equivalent to the digital signal processing means, the attenuated digital signal is converted to an analog signal by a D/A converter 14 equivalent to a D/A converting means. The analog signal is outputted through an amplifier 19 equivalent to an analog amplifying means. Thus, the overflowing is prevented and the clip of an output waveform can be prevented. COPYRIGHT: (C)1988,JPO&Japio | ||||||
| 328 | Method and apparatus for testing cell array processor chip | JP29507286 | 1986-12-12 | JPS62138936A | 1987-06-22 | SUTEIIBUN GUREGORII MOOTON |
| 329 | Device and method for generating time integral digital display of current | JP17294186 | 1986-07-24 | JPS6242068A | 1987-02-24 | PATORITSUKU ANSONII DAFUARUN |
| 330 | JPS627585B2 - | JP3121479 | 1979-03-19 | JPS627585B2 | 1987-02-18 | KAARU FUREDERITSUKU BAANHAATO |
| 331 | D/a converter | JP13164486 | 1986-06-06 | JPS61293024A | 1986-12-23 | HAMITSUDO DAGUHIGUHIAN |
| A D/A/ converter for use in a microprocessor comprises first and second timers (3A, 3B), first and second modulus latches (2A, 2B) associated respectively with said first and second timers for holding respective digital values, the timers being arranged to produce first and second respective overflow signals (4A, 4B) at predetermined counts, wherein said second overflow signal (4B) causes said first and second timers (3A, 3B) to be reset to the digital values held in said respective latches (2A, 2B), and bistable means (6) for receiving said overflow signals and producing an output at a first level in response to said first overflow signal and at a second level in response to said second overflow signal, whereby the pulses so produced form a pulse width modulated signal whose duty cycle is representative of the ratio of said respective digital values held in said respective latches. | ||||||
| 332 | Multiplex arithmetic type digital-analog converter | JP496185 | 1985-01-17 | JPS61164338A | 1986-07-25 | YASUNAGA SOICHIRO |
| PURPOSE: To attain various functions such as addition, subtraction, compensation or coincidence detection in addition to D/A conversion by constituting parallel resistors of a ladder type resistance circuit of plural pcs., and applying digital control so that they attain to L or H level, respectively. CONSTITUTION: N sets of resistors R2 1∼R2N having a resistance R are connected to other end of a termination resistor R 0 having a resistance value 2R whose one end is connected to a reference potential, one end of n-set of resistors R1 01∼R1 0n∼R1N 1∼R1N n having a resistance value 2nR is connected to both ends of a series resistance circuit comprising the N-set of resistors and each resistance connecting point, and switch circuits S 01∼S 0n∼SN 1∼SN n controlled by a digital signal are connected to the other end. In acting the circuit like an adder, n-set being a number of addition signals is prepared for the resistors R 10∼R 1N of each digit and the corresponding switch circuits S 01∼S 0n∼SN 1∼SN n are controlled by a corresponding digital signal to be added. In acting the circuit like a subtractor, n-set being number of input signals of the resistors R1 0∼R 1N is prepared for each digit, and a digital signal for the switches S 0∼SN corre sponding to a negative signal is applied via an inverter. COPYRIGHT: (C)1986,JPO&Japio | ||||||
| 333 | Ic device | JP14565684 | 1984-07-13 | JPS6125229A | 1986-02-04 | MORISONO MASAHIKO; MOGI HISAO |
| PURPOSE: To standardize a control system by applying an IC device to an electronic apparatus incorporating an inner bus system and therefore controlling the peripheral circuit of the IC device from the outside of the apparatus. CONSTITUTION: A CPU4 and a memory 5 are provided into an electronic apparatus 1 together with the 1st and 2nd IC devices 2 and 3. These CPU4 and the memory 5 are connected to each other via a bus line 6. The line 6 is connected to a connector 7 and a control computer 8 is connected to the connector 7 via a bus line 22. Thus the digital data on the control value is supplied to the devices 2 and 3 via the line 22, the connector 7 and the line 6 when the control is performed in a production mode. Then the device 2 gives the data to circuits AWE via an A/D converter 11 and selects the output signal through a switch circuit 12. The result of the control is displayed at a display part 9 from the computer 8. While peripheral circuits FWH are also controlled and displayed in the same way. These control values are stored in the memory 5 in the form of the reference value. COPYRIGHT: (C)1986,JPO&Japio | ||||||
| 334 | Analog signal processor | JP12908385 | 1985-06-13 | JPS6112124A | 1986-01-20 | PENNEY BRUCE J |
| 335 | Two input analog signal dividing system | JP24036583 | 1983-12-20 | JPS60132275A | 1985-07-15 | HATA FUSAO |
| PURPOSE:To improve an S/N and an accuracy of a division output by constituting so that the gain of the other lock-in amplifier is not varied, even if the gain of one lock-in amplifier is varied, due to a fact that one input of the lock-in amplifier to two analog inputs has become excessive. CONSTITUTION:Information from lock-in amplifiers (LA1, LA2)1 is inputted to a microprocessor 4, also a converting command clock is sent out of a converting clock generator 31, and an A/D conversion processing of an output of the lock- in amplifier 1 is executed by synchronizing with a conversion timing of an A/D converter 3. If the gain of the lock-in amplifier (LA1)1 becomes, for instance, 1/10 due to an excessive input, the microprocessor 4 sets a value of said converting input to 10 times by gain information of the lock-in amplifier concerned (LA1)1, when an A/D converted value (P) of an output 1 has been read, and executes a control so as to execute a division (DELTAP/P) to an A/D converted value (DELTAP) of an output 2. | ||||||
| 336 | Method and device for analyzing audio frequency | JP22111284 | 1984-10-18 | JPS60111120A | 1985-06-17 | JIERARUDO AARU SUTANRII |
| 337 | Stable sinusoidal wave generator | JP12290284 | 1984-06-13 | JPS6012804A | 1985-01-23 | RUISU GENARO OTSUTOBURU; ANDORASU IMURE ZABO; UYU SHI SHIYANGU |
| 338 | Digital signal processing circuit | JP9507983 | 1983-05-31 | JPS59221079A | 1984-12-12 | HARADA SHIGERU |
| PURPOSE:To reduce noises in an arithmetic processing mode and to ensure the effective contour emphasis processing by adding ''1'' to the lowest bit when the operated digital code signal is set at the negative value and rounding the code signal into a prescribed number of bits. CONSTITUTION:A differentiation circuit 11 of a digital signal processing circuit detects the edge part of a video signal. The video signal is converted into a digital code signal by a mid-trade type A/D converter 12. This code signal is applied to a signal processing circuit 13 containing arithmetic circuits 13a and 13b and a rounding correcting circuit 13s. Then ''1'' is added to the lowest bit if the code signal underwent the processing of circuits 13a and 13b is set at the negative value. Then the code signal is rounded by the circuit 13s. The output of the circuit 13 is converted into an analog output by a D/A converter 14 and added with the input analog signal by an adder 15. The noises are reduced in an arithmetic process of a negative code. Thus the effective contour emphasis processing is carried out. | ||||||
| 339 | Multiplication/addition circuit | JP9087683 | 1983-05-25 | JPS59192295A | 1984-10-31 | GIDEON AMIIRU; RUUBITSUKU GUREGORIAN |
| This invention provides a uniquely designed switched capacitor multiplier/adder (129) which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit significantly reduces the space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This size reduction in turn significantly reduces the manufacturing costs for this circuit over prior art circuits, and additionally allows the option of including on the speech synthesis chip a memory for the storage of binary representations of to-be-synthesized speech patterns. <??>In one embodiment of this invention, a novel structure and method are provided which minimize error components in the synthesized speech signal due to voltage errors inherent in the use of analog sample and hold circuits which are used to store the forward and backward prediction errors utilized in the linear predictive coding technique. | ||||||
| 340 | Interpolating device | JP16205882 | 1982-09-17 | JPS5952379A | 1984-03-26 | SHIMIZU KIYOUICHI |
| PURPOSE:To speed up drawing by calculating a picture drawing address by an interpolating device that works as a single function interpolating arithmetic unit constituting hardware. CONSTITUTION:The difference DELTAY of the coordinate values between vertexes corresponding to the first picture data is inputted to a DA converter 1 and an analog voltage corresponding to the difference DELTAY of the coordinate values between DA converted vertexes is outputted. The outputted analog voltage is inputted to a resistance ladder 4 through an electronic switch 2 whose connection position is selected and changed by a multiplexer driver 3 to which the difference DELTAX of the coordinate values between the verteses corresponding to the second picture data is inputted. The analog voltage analog processed by the resistance ladder 4 is connected to an AD converter 7 through an electronic switch 5 whose connection position is selected and changed by a multiplexer driver 6 to which the scanning address variable N of a side connecting vertexes is inputted, and supplied to the AD converter 7 as the analog voltage conforming to the connection position of the electronic switch 5. | ||||||
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