Le circuit comprend deux modules multiplicateurs (M1, M2) comprenant chacun au moins un potentiomètre (P1, P2) commandable pour régler le rapport d'amplitude entre un signal de sortie (Vs, V'2) et un signal d'entrée (V1, Vr) du module. Les potentiomètres ont des caractéristiques sensiblement identiques et sont commandés de la même manière de sorte que les rapports d'amplitude des modules multipli- cateurs sont sensiblement égaux. L'un des modules (M1) reçoit comme signal d'entrée le premier signal à multiplier (V1) et délivre un signal de sortie (Vs) proportionnel au produit des deux opérandes, tandis que l'autre module (M2) reçoit comme signal d'entrée une tension de référence (Vr) et délivre comme signal de sortie un signal de rétroaction (V'2) qui est asservi à une valeur approximativement égale à celle du second signal à multiplier (V2).

Utilisation dans des compteurs d'énergie électrique.

In order to implement high resolution A/D (or D/A) conversion, the differentiated waveform of an analogue (or digital) waveform signal is generated by a differentiated waveform generating unit (10). The differentiated waveform is cyclically distributed at the timings of clock signals (CK₀) to integrators (14₁ to 14_N) (N is an integer of 2 or more). These integrated outputs are converted into digital (or analogue) signals by converters (15₁ to 15_N). These converted outputs are added by an adder (16). The added result is output as a digital (or analogue) waveform signal.

. A noise generating device is provided which includes a pseudo-random number generator having a shift register that performs shift operations to sequentially shift the bit in the input stage to the next higher significant stage and an exclusive-OR circuit that XORs a plurality of bits from selected stages of the shift register and feeds back to the first stage of the shift register, and an analog filter having an analog element that limits the band of digital data created from the bits in the shift register of the pseudo-random generator and outputs as an analog signal.

A multiplying digital-to-analogue converter is of the kind in which digitally weighted currents proportional to a voltage applied to an analogue input (19) are generated at respective outputs (3) of a current mirror arrangement (1), these currents being switched to an output (9) in accordance with the value of a digital signal applied to a digital input (11). In order that the converter can accommodate analogue input voltage of either polarity relative to ground and generate corresponding output currents a bias current is applied to the current mirror input (2) from a current source (15). This results in digitally weighted bias currents being generated at the current mirror outputs (3). These bias currents are offset by corresponding bias currents generated at respective outputs (6) of a second current mirror arrangement (4).

The signal multiplier device SMD multiplies two signals I1 and I2 applied to its input terminals and generates a digital pulse signal OUT proportional to the result of this multiplicaiton at a terminal OUT. It includes a first pulse density modulator PDM1 converting I1 to a 1-bit word signal C which controls a switch S to connect I2 either directly or via an invertor I to an input of a second pulse density modulator PDM2, depending on the value of C.

The device can be included in a device, e.g. an electric energy meter to measure the integral of the product of I1 and I2 or the power of an electric power signal in case of an electric energy meter, in which case I1 is the voltage signal of the electrical power signal, whilst I2 is the current signal or vice-versa. The number of pulses of the digital pulse signal OUT generated during a predetermined time interval is indicative of the power consumption of a user receiver the electric power signal via the meter.

A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.

An apparatus adaptable for use with a digital-analog conversion device for effecting communications from a digital device to an analog device, having a digital-analog circuit for converting interpolated outgoing digital signals to outgoing analog signals. The apparatus further has a digital signal processing circuit for interpolating outgoing digital signals received from the digital device and providing an interpolated outgoing digital signal to the digital-analog device.

The digital signal processing circuit is comprised of a plurality of modules which are configured so that a specified set of the plurality of modules effects a specified number of iterations of interpolation. The modules are further designed so that additional modules may be added to the specified set of modules to increase the iterations of interpolation.

A method for operating an apparatus for facilitating communications between an analog device and a digital device, which apparatus includes a plurality of signal processing circuits and a control circuit for controlling the signal processing circuits. Each of the signal processing circuits includes signal attenuators and signal burst discrimination circuitry. The apparatus is operable in a plurality of stable states, preferably in an idle stable state, a transmit stable state, and a receive stable state. The apparatus also is operable in a plurality of transitional states, including up-transition states and down-transition states. The method includes the steps of evaluating each of the signal processing circuits by the signal burst discrimination circuitry, responding to detection of a burst indicator by setting a state indicator to an appropriate up-transition state, incrementally adjusting the attenuators in the signal processing circuits to enhance performance of the apparatus until the attenuators are at predetermined settings, periodically checking for presence of the burst indicator, on detection of cessation of the burst indicator, setting the state indicator to an appropriate down-transition state, incrementally adjusting the attenuators to redistribute attenuation losses among the signal processing circuits, if no burst indicator is detected, continuing such redistribution until the apparatus returns to the idle stable state.

Waveform data read out of a memory (12) is converted by a D/A converter (13) into an analog waveform, which is amplified by an amplifier (15), from which a waveform signal is generated. To cancel the generation of a distortion in the amplifier, a composite waveform composed of a distortion canceling signal waveform and a fundamental frequency signal waveform to be generated is written into the memory. To determine a distortion canceling signal, the fundamental frequency component in the signal waveform which is output from the amplifier when multi-sine waveform data is read out of the memory, is attenuated by a notch filter (17), and the signal waveform is converted by an A/D converter (18) to a digital multi-sine waveform, which is provided to a computation and control part (10) and subjected to a Fourier transform analysis to compute the amplitude and phase of each harmonic component. Further, the output of the amplifier when fundamental frequency sine waveform data is read out of the memory, is fed via the notch filter and the A/D converter to the computation and control part, wherein it is subjected to a Fourier transform analysis to compute the amplitude and phase of each distortion component. At the same time, the output of the amplifier is converted into digital waveform data without being applied to the notch filter and the data is subjected to a Fourier transform analysis in the computation and control part. By this, the amplitude and phase of the fundamental frequency component are computed. Based on the results of these Fourier transform analyses, the amplitude and phase of each frequency component of the distortion canceling signal are determined, which are used to compute composite waveform data composed of the distortion canceling signal and the fundamental frequency signal.

A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.

An emulation system used to debug software for a digital signal process (DSP) (6) includes a built-in digital signal analyzer (18) which operates upon the same digital signals as those presented directly to and outputted by the DSP (6), bypassing the signal converters (4, 8) used to convert an input analog signal to digital format and the output digital signal to analog format. A host computer (12) communicates with the digital signal analyzer (18) via firmware in a control processor (30) and personality board (36), or is alternately connected directly with the analyzer (18). Communications between the digital signal analyzer and the DSP (6) are through the same contact probe (14) as that used for the emulation software. The analyzer may be used to trigger a software function within the emulator (20) based upon the real-time signal from the DSP (6), and is also capable of interpolating between successive digital values of an analyzed signal for display purposes.

A hybrid monolithic IC that is standardized for controlling various types of electrical equipment, such as circuit breakers, motor controllers and the like. The IC is a hybrid monolithic IC, fabricated in CMOS technology. The IC includes an on-board microprocessor (30), an A/D subsystem (64) and various input/output devices which make it adaptable for use in various types of electrical equipment. In order to improve the resolution of the A/D subsystem, circuitry is provided, which includes current and voltage ranging amplifiers for ranging analog input voltage and current signals and compensating internal offsets, in such amplifiers, inherent in CMOS linear circuits which can affect the accuracy of the least significant bit. Novel auto-zero circuitry is provided for controlling the offsets in the ranging amplifiers.

An electrical overcurrent circuit provides both digital based modeling and analog based modeling of the temperature of an electrical conductor to simulate the conductor temperature during all expected operating conditions including a condition when electrical power is unavailable to the electrical overcurrent circuitry.

An operational circuit device for calculating a plurality of bit data includes, an input unit for inputting a plurality of bit data, a constant current source provided for each of the plurality of bit data for generating a predetermined current in accordance with the bit data inputted from the input unit and a calculation unit for calculating a sum of the predetermined currents from the constant current sources.

A one-chip semiconductor integrated circuit device includes a digital signal processing circuit (2) which processes a digital signal in synchronism with a first clock signal (CK1), and an analog signal processing circuit (3) which samples an analog input signal in synchronism with a second clock signal (CK2) having a phase different from that of said first clock signal.

A control circuit comprising an addressable memory device which has an address ranged addressed by n address inputs of the device, the address inputs are divided into two groups each comprising address inputs and each word written in the memory is pre-programmed to provide an output when addressed by n digital inputs which output depends upon an effective comparison between the two groups of digital inputs present.

Zur getrennten Prüfung der analogen Schaltkreise und der digitalen Schaltkreise werden in die Leitungen, die die analogen und digitalen Schaltkreise miteinander verbinden, Trennzellen (TZ) eingefügt, durch die diese Leitungen (VL1, VL2) unterbrechbar sind. Die Zufuhr der Testsignale zu den digitalen Schaltkreisen (DBL) bzw. zu den analogen Schalt­kreisen (ABL) kann ebenfalls über die Trennzellen (TZ) er­folgen. Dazu können die Trennzellen (TZ) zu einem Schiebere­gister zusammengeschaltet werden, dem über äußere Anschlüsse (PIN) Testsignale zugeführt werden bzw. von dem von den Schaltkreisen abgegebene Testsignale zu einem äußeren Anschluß (PN) übertragen werden. Weiterhin ist es möglich, daß die Trennzellen (TZ) unabhängig voneinander im Parallelbetrieb arbeiten und dabei in den Trennzellen gespeicherte Testsignale den Schaltkreisen (ABL, DBL) zuführen bzw. im parallelen Betrieb von diesen Schaltkreisen ab gegebene Testsignale übernehmen. Trennzellen, die mit den analogen Schaltkreisen (ABL) verbunden sind, weisen eine Ausgangsstufe auf, die sicherstellt, daß an den Eingängen der analogen Schaltkreise im Schiebebetrieb keine Änderungen auftreten. Weiterhin ist es möglich, den analogen Schaltkreisen (ABL) im Testbetrieb die Testsignale parallel von äußeren Anschlüssen (PIN), die im Normalbetrieb mit den digitalen Schaltkreisen (DBL) verbunden sind, direkt zuzuführen. Dazu können Testmultiplexer (TMUX) vorgesehen sein. Die Aufteilung der Schaltkreise in einen digitalen Block (DBL) und einen analogen Block (ABL) ist deswegen zweckmäßig, da dann die Entwicklung der zu verwen­denden Prüfprogramme wesentlich erleichtert wird.