Square root extractor circuits专利检索- 混合计算装置专利检索查询-专利查询网

Square root extractor circuits
申请号	EP83303725	申请日	1983-06-28	公开(公告)号	EP0099203A3	公开(公告)日	1986-02-12
申请人	THE BABCOCK & WILCOX COMPANY;			发明人	Keyes, Marion A.IV; Thompson, William L.;
摘要	A circuit (10) for extracting the square root of an incoming voltage signal utilizes a four-bit up/down counter (14) to control the output duty cycle of a pair of four-bit rate multipliers (16, 18) connected in a cascaded configuration. The output of the second rate multiplier (18), which is related to the square of the up/down counter value, is used to control the mode of the counter (14) so as to track the incoming voltage signal. Inasmuch as the square of the up/down counter value is tracking the incoming voltage signal, the output duty cycle of the first rate multiplier (16) in the cascaded pair is the square root of the incoming voltage signal which is subsequently converted into analog form. The circuit also utilizes a "dithering" technique so that the resulting square root output signal has greater than four-bit accuracy.
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