| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 301 | Digital data processing apparatus | JP26264984 | 1984-12-12 | JPH0687017B2 | 1994-11-02 | アーサー・エム・オルセン; ドール・ビー・ボザース，ジユニア セオ; ロナルド・エツチ・ローランズ |
| 302 | Frequency synthesizer | JP4859193 | 1993-02-15 | JPH06244639A | 1994-09-02 | MIYASHITA HIDEO; URIYA SUSUMU |
| PURPOSE: To provide a frequency synthesizer with simple configuration and high phase accuracy. CONSTITUTION: A saw-tooth-shaped wave signal generating circuit 3 generates a saw-tooth-shaped wave signal (d) corresponding to a timing signal (b) based on a reference clock (a). A voltage comparator 4 gets a synthesizer output (e) of a rectangular wave by slicing the inputted saw-tooth-shaped wave signal corresponding to a reference voltage and shaping the waveform. Each time the reference clock (a) is inputted, the count value of a counter 5 for adding or subtracting a fixed value is made analog by a DAC 6, that value is applied to the saw-tooth-shaped wave signal generating circuit 3 as a bias voltage and a voltage to start the rise or fall of the saw-tooth-shaped wave signal (d) is operated so that timing for the sawtooth-shaped wave signal (d) to be sliced at the voltage-comparator 4 can be arbitrarily prepared and the synthesizer output (e) can be provided at any arbitrary phase. COPYRIGHT: (C)1994,JPO&Japio | ||||||
| 303 | Scaler circuit | JP4204893 | 1993-02-05 | JPH06232650A | 1994-08-19 | KOTOBUKI KOKURIYOU; YOU IKOU; TAKATORI SUNAO; YAMAMOTO MAKOTO |
| PURPOSE:To obtain a circuit in which variable level adjustment is executed with high accuracy and the effect of offset is cancelled by executing multiplication based on the ratio of an input capacitance to a 1st stage feedback capacitance and cancelling an offset of a 1st stage inverter and an offset of a 2nd stage inverter. CONSTITUTION:A 1st stage coupling capacitor CPO1, a 1st stage inverter INV1, a 2nd stage coupling capacitor CPO2, a 2nd stage inverter INV2 are connected in series and an input voltage Vin is given to the 1st stage coupling capacitor CPO1. Plural feedback paths L21-L24 feeding back its input to an output are connected to the 1st stage inverter INV1 and capacitors C21-C24 are provided in the feedback paths L21-L24. Then the multiplication is executed based on the ratio of the input capacitors C11-C14 to the 1st stage feedback capacitors C21-C24 and an offset by the 1st stage inverter INV1 and that of the 2nd stage inverter INV2 are cancelled. | ||||||
| 304 | Multilying circuit | JP2067693 | 1993-01-13 | JPH06215164A | 1994-08-05 | KOTOBUKI KOKURIYOU; YOU IKOU; UIWATSUTO UONWARAUIPATSUTO; TAKATORI SUNAO; YAMAMOTO MAKOTO |
| PURPOSE: To provide the multiplying circuit which can directly multiply analog data and digital data without requiring A/D and D/A conversion. CONSTITUTION: Respective bits b 0-b 7 of digital data are divided into plural groups, and a group weight in proportion to a correspondent bit value is defined for each group. Then, for each bit in each group, the bit weight in proportion to the value is defined. Capacity coupling CP 1 and CP 2 are performed for analog data Vin through opening/closing means SW 0-SW 7 by capacitances C 0-C 7 with capacity in proportion to the bit weight, capacity coupling CP 3 is performed by capacitance C 22 and C 23 with capacity in proportion to the group weight of each group, and the opening/closing of the opening/closing means SW 0-SW 7 is controlled by the digital data. COPYRIGHT: (C)1994,JPO&Japio | ||||||
| 305 | Multiplying circuit | JP33000392 | 1992-11-16 | JPH06162230A | 1994-06-10 | UIWATSUTO UONWARAUIPATSUTO; YOU TADAYASU; KOTOBUKI KOKURIYOU; TAKATORI SUNAO; YAMAMOTO MAKOTO |
| PURPOSE:To provide the multiplying circuit which can execute multiplication of a small scale and high accuracy, and also, can execute highly accurate analog-to-digital multiplication. CONSTITUTION:By setting a digital input voltage as a switching signal, whether an analog input voltage X is generated in an output terminal Tout or not is controlled, and with respect to digital input signals B0, B1, B2, B3, B4, B5, B6 and B7 of plural bits, plural multiplying circuits M0, M1, M2, M3, M4, M5, M6 and M7 are provided in parallel, outputs VOout, V1out, V2out, V3out, V4out, V5out, V6out and V7out of each multiplying circuit are integrated by capacity coupling CP, and in this capacity coupling, weight corresponding to weight of digital input voltages B0, B1, B2, B3, B4, B5, B6 and B7 of each multiplying circuit is given. | ||||||
| 306 | Sine wave oscillator | JP29592188 | 1988-11-22 | JPH0624288B2 | 1994-03-30 | BERUNERU MITSUTERUMAIERU; ERUBIN BIIBURU; TOOMASU MAUKUSHU |
| 307 | Analog signal processing unit | JP12908385 | 1985-06-13 | JPH0614615B2 | 1994-02-23 | BURUUSU JEI PENII |
| 308 | Integrated circuit having analog and digital parts and including thermal modelling | JP36047191 | 1991-12-31 | JPH0645934A | 1994-02-18 | ROBAATO TOREISHII ERUMUZU; JIYOSEFU CHIYAARUSU ENGERU; JIYON KAARU SHIYUROTSUTARAA; UIRIAMU JIYON MAAFUII |
| PURPOSE: To provide a CMOS-IC, including various input output devices by providing a current/voltage range decision amplifier circuit to a CMOS linear circuit and allowing an overcurrent circuit to conduct D/A modeling of a conductor temperature, so as to simulate a conductor temperature. CONSTITUTION: A current and voltage action of input channels 62, 64 is controlled by multiplexers MUX 66, 68 selected by the software. The channels 62, 64 receive a positive voltage of 0 to 2.5Vdc, which is fed to a variable gain amplifier 8 capable of automatic zero processing. The signals are processed in the automatic range decision mode or in the fixed gain mode, depending on the selection by the software. A power supply from an overcurrent circuit is obtained by a sensing load current or a circuit interrupter output. Since the overcurrent circuit includes both a digital base model and an analog base model, even when a power supply of the overcurrent circuit is lost, this circuit simulates a conductor temperature. As a result, the CMOS-IC, including various input output devices that convert an analog voltage current signal into a digital signal, is obtained. | ||||||
| 309 | Reducing method for spurious signal generated from digital signal processor | JP9985793 | 1993-04-26 | JPH0629842A | 1994-02-04 | HILPERT THOMAS DIPL-ING; MUELLER STEFAN DIPL-ING; BECHER JUERGEN; GEHRIG WILFRIED W |
| PURPOSE: To reduce spurious signals which are produced by changes of power consumption due to the cyclic operation of a processor. CONSTITUTION: A digital signal processor that depends on a command code to be executed carries out a circulatively repeated program routine BP which is initialized by an interrupt INT. A 1st mean power consumption Im is produced for an operation time, and the operating time, which is shorter than a time between two continuous interrupts, of the routine BP is produced by power consumption of the digital signal processor. The processor performs a waiting routine AWAIT that produces mean power consumption of the processor which corresponds to the consumption Im in the program routine period between continuous program routines BP. | ||||||
| 310 | User-configurable integrated circuit structure | JP5948892 | 1992-02-13 | JPH05267458A | 1993-10-15 | Khaled A El-Ayat; カーレツド・エイ・エル・アイアト |
| PURPOSE: To provide a user-programmable integrated circuit containing analog parts including user-configurable analog circuit modules, digital parts including user-configurable digital circuit modules, interface parts including user- configurable interface circuits for the A/D and D/A conversions of signals, user-configurable interconnections and input/output structures. CONSTITUTION: A user-programmable integrated circuit comprises analog parts 12a-12d including user-configurable analog circuit modules, digital parts, including user-configurable digital circuit modules 14a-14f, interface parts 16a, 16b including user-configurable interface circuits for the AD and DA conversions of signals, user-configurable interconnections 36-56 and input/output structures 18a-18l. | ||||||
| 311 | Pwm circuit | JP2054092 | 1992-01-08 | JPH05191238A | 1993-07-30 | MURAKAMI DAISUKE; YOSHIDA HIDEKI |
| PURPOSE: To provide the PWM circuit with an excellent linearity in an input level versus pulse width characteristic. CONSTITUTION: A delay clock DOUT which is delayed by a delay time in response to a level of an input analog voltage VIN is obtained by using an A/D converter 4 converting an input analog voltage VIN into a digital voltage, and a delay circuit 9 with an excellent linearity in which the relation between number of stages of delay gates 5, 5... to be passed through and the delay time is proportional to each other. Then an RS flip-flop 12 generates a pulse signal OUT having a pulse width corresponding to the delay time after the clock CK2 is given till the delay clock pour is given. COPYRIGHT: (C)1993,JPO&Japio | ||||||
| 312 | JPH0521246B2 - | JP14565784 | 1984-07-13 | JPH0521246B2 | 1993-03-23 | MORISONO MASAHIKO; MOGI HISAO |
| 313 | Real time signal analyzing and method therefor device for digital signal processor emulation | JP1748092 | 1992-02-03 | JPH0553859A | 1993-03-05 | KEBUIN DABURIYUU REARII; RATSUSERU ERU RIBUIN |
| PURPOSE: To provide an emulation system used for debugging a software for a digital signal processor including a digital signal analyzer. CONSTITUTION: A host computer 12 communicates with the digital signal analyzer 18 through a control processor and a personality board, or is directly connected to the analyzer 18. Communication between the digital signal analyzer means and a digital signal processor 6 user the same contact probe 14 as the one used for an emulation software. The analyzer is used to trigger a software in an emulator 20, based on real-time signal from the digital signal processor 6, and is also able to interpolate between the analyzed signals for display purpose or and between a same continuous digital values. | ||||||
| 314 | Method for actuating device used for making communication between analog device and digital device easier | JP24805891 | 1991-09-26 | JPH04284045A | 1992-10-08 | ARAN EFU HENDORIKUSON; HAABAATO EMU CHIEN; KAARIN DORIYU KABURAA; RAJIBU HATSUTANGADEI |
| PURPOSE: To provide a device which is used for making the communication between an analog device and a digital device easier. CONSTITUTION: A device used for making communication between analog device and digital device easier is composed of a transmission circuit 12, a reception circuit 14, and a control circuit 16. The circuit 12 outputs analog signals received through an input 18 as compressed digital signals from an output 26 and the circuit 14 sends compressed digital signals from an input 34 through an output circuit 44 after converting the signals into analog signals. A hand-free control circuit 54 respectively receives transmitting and received signal level information through transmitting and received speech detectors 60 and 62 and uses the information for the decision of the attenuating amounts of attenuators 30, 32, 50, and 52. A stable transmitting state is obtained when the attenuating amounts of the circuits 12 and 14 are respectively set at the maximum and minimum and a stable receiving state is obtained when the attenuating amounts of the circuits 12 and 14 are oppositely set. In addition, a stable idling state is obtained when the attenuating amounts of the circuit 12 and 14 are made equal to each other. In addition, four shifting states which make sure the smooth shifting among the three stable states are provided. COPYRIGHT: (C)1992,JPO | ||||||
| 315 | Signal processor using neural net | JP5405591 | 1991-02-26 | JPH04271459A | 1992-09-28 | KUWATA RYUICHI |
| PURPOSE: To execute inference and control by means of a production rule at high speed by utilizing the parallel processing of a neural net and instantly selecting a reference signal which has a nearest size with an input signal. CONSTITUTION: N-number reference analog signals Ai are generated from a reference analog signal generating element 3 and signal-conversion is executed to an unknown analog input signal X in such a way that the nearest one of the reference signals Ai to the input signal becomes a largest value through the use of a compliment element 4. The converted signal is inputted to a neural net 1 which detects a largest input so as to detect the reference signal Ai which is nearest to the input X. A class is judged so as to be linearized and inference and control are executed in accordance with the class by adding a correction element, inference and control to the neural net 1. COPYRIGHT: (C)1992,JPO&Japio | ||||||
| 316 | Arithmetic unit | JP55791 | 1991-01-08 | JPH04251389A | 1992-09-07 | TATENO TETSUYA |
| PURPOSE:To obtain an arithmetic unit which does not use any digital arithmetic circuit as the arithmetic unit for making arithmetic operations on plural digital signals and outputs obtained results in the form of analog signals. CONSTITUTION:Constant-current sources 19-26 are connected to switches 11-18 which open and close in accordance with input digital signals. The current sources 19-26 are provided at every input bit and connected so that electric currents can be added at every item of the input bits. The currents added at every item are inputted to a resistance ladder 9 and the ladder 9 outputs output voltages corresponding to the inputted currents. | ||||||
| 317 | JPH0376494B2 - | JP12706583 | 1983-07-14 | JPH0376494B2 | 1991-12-05 | CHETSUTO JEI SURABINSUKI |
| 318 | Digital mixer | JP22521589 | 1989-08-31 | JPH0388508A | 1991-04-12 | HAMAMATSU HIROSHI |
| PURPOSE: To mix many channels with a small number of conductors by providing an analog adding means, an A/D converting means, and a digital adding means, and performing the analog addition of parallel input data of plural channels through buses so that corresponding bits are added. CONSTITUTION: Bit output currents of channel modules 34-1-34-N are passed through buses 40.0-34.23 as analog adding means and the corresponding bits are added by analog. The respective current values after the analog addition are converted into voltage values, which are converted into digital signals by A/D converters 46.0-46.23. Then addition data of the respective bits is matched in their digits by a digital addition circuit 48 and are added mutually and respective bit signals of final digital mixing outputs are outputted from output terminals 50.0-50.23. Therefore, when the number of output bits of the A/D converter 46 is M, channel modules of 2M channels can be connected. COPYRIGHT: (C)1991,JPO&Japio | ||||||
| 319 | Signal processing circuit for multiplication | JP16760489 | 1989-06-29 | JPH0332212A | 1991-02-12 | TAKEUCHI SUMITAKA; KONO HIROYUKI |
| PURPOSE: To attain high speed multiplication processing by generating a control signal based on a multiplication coefficient, representing the multiplication coefficient as a decimal form, applying gate processing based on the control signal and converting the signal into a signal representing the result of multiplication. CONSTITUTION: A control signal generating circuit 52 generates prescribed one or plural control signals among plural kinds of control signals prepared in advance in response to a digital signal Ca from a digital signal input circuit 51. The control signal generated from the control signal generating circuit 52 represents a multiplication coefficient Ca in terms of a decimal number. A multiplication decode circuit 53 applies signal conversion to an input digital signal X from an input terminal 1a based on a control signal from the control signal generating circuit 52, converts the result into a signal representing the multiplication between the digital signals X and Ca and the result is outputted. An analog signal output circuit 54 supplies a current to a signal representing the multiplication result from a multiplication decode circuit 53. Thus, fast speed multiplication is attained. COPYRIGHT: (C)1991,JPO&Japio | ||||||
| 320 | Document retrieval device | JP14843889 | 1989-06-13 | JPH0314075A | 1991-01-22 | MORITA TETSUYA |
| PURPOSE: To speed up the operation of the document retrieval device greatly by finding the evaluated value of each document by an analog arithmetic means by using key word relativity indicating the strength of relation between key words and the relation between key words and the document. CONSTITUTION: This device is provided with a 1st storage means 10 which holds the strength of relation between key words, a 2nd storage means 12 which holds the relation between key words and documents, and a key word connection selecting means 4 which selects a key word connection according to retrieval conditions and converts it into an analog signal. Further, the device is provided with analog arithmetic means 16-1 - 16-m which calculate document likelihood by using the value of the key word connection in the form of the analog signal and converting means 18-1 - 18-m which convert the calculated document likelihood into a digital value. Consequently, the document likelihood is calculated by an analog circuit and fuzzy retrieval is performed fast. COPYRIGHT: (C)1991,JPO&Japio | ||||||
QQ群二维码
意见反馈
意见反馈