BACKGROUND AND SUMMARY

The invention provides a solar cell generating alternating current in response to light. A central region of given conductivity type semiconductor material is disposed between first and second regions of intrinsic or invertable semiconductor material. AC gate driver means alternates the induced polarity type in the intrinsic or invertable regions such that hole-electron pairs generated by light radiation diffuse alternately and in opposite directions between the alternately generated pn junctions between the central region and the respective first and second intrinsic or invertable regions, thus generating alternating current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic substrate circuit diagram illustrating an AC solar cell constructed in accordance with the invention.

FIG. 2 is a schematic substrate circuit diagram showing an alternate embodiment of FIG. 1.

FIG. 3 is a top view of a portion of FIG. 2.

FIG. 4 is a view like FIG. 3, showing an alternate embodiment.

DETAILED DESCRIPTION

There is shown in FIG. 1 an AC solar cell 2 having a central region 4 of given conductivity type semiconductor material, such as n type, between first and second regions 6 and 8 of intrinsic or invertable semiconductor material. Regions 6 and 8 may be separate, or part of a common substrate layer 10. First and second gate electrodes G₁ and G₂ are provided for respective first and second intrinsic or invertable regions 6 and 8. AC gate driver means 12 is provided for applying alternating polarity gate potential to the first and second gate electrodes. During the first half cycle, first intrinsic or invertable region 6 is converted to one conductivity type and second intrinsic or invertable region 8 is converted to the opposite conductivity type. During the second half cycle, first intrinsic or invertable region 6 is converted to the opposite conductivity type and second intrinsic or invertable region 8 is converted to the one conductivity type.

First and second terminal connection means 14 and 16 are provided for the first and second intrinsic or invertable regions 6 and 8. During the first half cycle, hole-electron pairs, generated by light radiation impinging the top surface of cell 2, diffuse across the pn junction between the central region 4 and one of the converted intrinsic or invertable regions 6 and 8 to set up a potential gradient which drives current in one direction between first and second terminal connection means 14 and 16. During the second half cycle, hole-electron pairs generated by light radiation diffuse across the pn junction between central region 4 and the other of converted intrinsic or invertable regions 6 and 8 to set up a potential gradient which drives current in the opposite direction between first and second terminal connection means 14 and 16. There is thus generated alternating current between first and second terminal connection means 14 and 16 for driving an external load 18.

FIG. 2 shows an alternate embodiment, and like reference numerals are used where appropriate to facilitate clarity. In cell 20 of FIG. 2, first and second terminal connection means 14 and 16 include regions 22 and 24 of degenerately doped semiconductor material each forming a nonblocking junction with its respective intrinsic or invertable region 6 or 8 regardless of whether the latter is converted to p or n type. First and second terminal connection means 14 and 16 further include respective terminals T₁ and T₂ contacting respective degenerate regions 22 and 24. Degenerate regions 22 and 24 are the same conductivity type as central region 4, such as n type.

In preferred form, in both embodiments, first and second intrinsic regions 6 and 8 are part of a common substrate 10 having a tub 4 of given conductivity type semiconductor material formed therein to provide the central region. First and second gate electrodes G₁ and G₂ are preferably proximate and insulated from respective first and second intrinsic or invertable regions 6 and 8, though the gate electrodes may contact the intrinsic or invertable regions if desired. In preferred form, gate electrodes G₁ and G₂ are insulated from intrinsic or invertable regions 6 and 8 by transparent insulation material 26 extending across central region 4 along the top surface of the cell. Central region 4 and first and second intrinsic or invertable regions 6 and 8 are coplanar along top major surface 28 of the cell. First and second intrinsic or invertable regions 6 and 8 are formed by common substrate 10 extending upwardly on left and right sides of central region 4 to top major surface 28.

In FIG. 2, a first terminal connection means 14 comprises tub region 22 of degenerately doped semiconductor material formed in substrate 10 from top major surface 28 and spaced leftwardly from central region 4 by first intrinsic or invertable region 6 of substrate 10 extending upwardly therebetween to top major surface 28. First degenerate tub region 22 forms a nonblocking junction with first intrinsic or invertable region 6 regardless of whether the latter is converted to p or n type by first gate electrode G₁ during the respective half cycle of gate driver means 12. First terminal connection means 14 further comprises first terminal T₁ contacting first degenerate tub region 22. Second terminal connection means 16 comprises second tub region 24 of degenerately doped semiconductor material formed in substrate 10 from top major surface 28 and spaced rightwardly from central region 4 by second intrinsic or invertable region 8 of substrate 10 extending upwardly therebetween to top major surface 28. Second degenerate tub region 24 forms a nonblocking junction with second intrinsic or invertable region 8 regardless of whether the latter is converted to p or n type by second gate electrode G₂ during the respective half cycle of gate driver means 12. Second terminal connection means 16 further comprises second terminal T₂ contacting second degenerate tub region 24.

FIG. 3 shows a partial top view of n region 22 of FIG. 2, illustrating that region 22 extends laterally in the form of a bar or the like. FIG. 4 shows an alternate embodiment wherein bar region 22 is replaced by a plurality of alternating n+ and p+ regions such as 31-37. When using the structure in FIG. 4, region 6 of FIG. 2 need not be as heavily accumulated or depleted, which is otherwise desirable for providing the degenerate diode between regions 22 and 6, Region 10 in FIGS. 1 and 2 can be a polycrystalline layer over an insulating substrate, or a single crystal layer over an insulating substrate. Region 10 may be p type if invertable in areas 6 and 8 to n type. If region 10 in FIG. 1 is p type, it may be desirable to provide n regions such as 22 and 24 under main terminal metallizations T₁ and T₂ in FIG. 1. If region 10 in FIG. 2 is p type, the alternative of FIG. 4 is not used.

It is recognized that various modifications are possible within the scope of the appended claims.