专利汇可以提供ALL DIGITAL PHASE LOCKED LOOP专利检索,专利查询,专利分析的服务。并且The present invention relates to an all-digital Phase-Locked Loop comprising - a reference phase generator (PHR) arranged for receiving a digital signal and for splitting the digital signal into an integer part (PHR_I) and a fractional part (PHR_F), - an estimator block (20) arranged for estimating a control signal, - a digital-to-time converter (30) arranged for receiving the estimated control signal and a reference clock signal (FREF) and arranged for deriving a delayed reference clock signal () using the reference clock signal and the estimated control signal, - a time-to-digital converter (40) arranged for receiving the delayed reference clock signal and a desired clock signal phase () and for deriving a fractional phase error, characterised in that the estimator block is arranged for receiving the fractional phase error and for determining the estimated control signal by * correlating the fractional phase error with a version () of said fractional part having zero mean, yielding a correlated signal (), * multiplying the correlated signal with its absolute value, * integrating the outcome () of said multiplying to so obtain the estimated control signal.,下面是ALL DIGITAL PHASE LOCKED LOOP专利的具体信息内容。
The present invention is generally related to the field of all digital loops for use in various types of low power, high performance applications.
In recent years one has seen a proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits in terms of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability and amenability to integration with digital baseband and application processors. All-digital PLLs have been proposed to achieve savings in both the area cost and the power dissipation. Compared to analog PLLs, all-digital PLLs (ADPLLs) are preferred in nanoscale CMOS as they dramatically reduce the chip area and further also offer benefits of programmability, capability of extensive self-calibrations and easy portability. In this way power-efficient wireless applications can be envisaged. As the ADPLLs are now employed in high-volume consumer applications, there is a continuous push to provide high performance at low cost and low power consumption.
One substantial problem with conventional ADPLLs is due to the fact that the time-to-digital-converter (TDC) of an ADPLL is traditionally power hungry. In the time domain, the time-to-digital converter acts as phase detector to compare the phase leading/lagging of the input reference clock signal and the output high frequency clock signal.
In low power all digital phased locked loops (AD-PLL) the clock edges of the digitally controlled oscillator (DCO) are retimed via a delay-to-time converter (DTC), such that that power hungry time-to-digital-converter (TDC) can be reduced in size. However, the actual delay of the elements of a DTC is a function of the process power supply voltage and temperature (PVT). These variations are in the order of ±20% of the designed delay. Therefore the delay elements need to be calibrated as a misaligned DTC causes degradation of the performance and in some cases renders the AD-PLL inoperable. Conventional calibration algorithms require long settling times and do not converge for small fractional settings.
An example of the traditional approach centred around a time-to-digital-converter is found in the paper "
A simplified block diagram of the applied gain estimation algorithm is shown in
The technique proposed in this paper however suffers from long convergence times (200 µs and more). Such a calibration time makes it unsuitable for fast frequency switching in, for example, an architecture as used in a Bluetooth low Energy radio where transmit and receive switching requires the PLL to jump 500 MHz between transmitter and receiver. Moreover, this solution often is very unstable at small fractional settings where it may not converge at all. An illustration of the stability problem at small fractional parts is provided in
Another example of an All-digital phase-locked loop including a TDC and a gain estimation method controlling a DTC which provides a delayed reference clock to the TDC is disclosed by the patent application publication
Hence, there is a need for an approach wherein this drawback is avoided or overcome.
It is an object of embodiments of the present invention to provide for an all-digital PLL (AD-PLL) arranged for calibrating a delay line in the AD-PLL in such a way that long settling times are avoided and wherein small fractional ratios between the RF carrier and the reference clock can be dealt with.
The above objective is accomplished by the solution according to the present invention.
In a first aspect the invention relates to an all-digital Phase-Locked Loop comprising
characterised in that said estimator block is arranged for receiving said fractional phase error and for determining said estimated control signal by
The proposed solution indeed allows for avoiding long settling times and for properly dealing with small fractional ratios between the RF carrier and the reference clock. In order to estimate a control signal to steer the calibration of the time-to-digital converter in the AD-PLL the invention proposes the use of an algorithm wherein the correlated signal is multiplied with its absolute value in the process of determining the control signal estimation. Doing so considerably improves the performance.
In a preferred embodiment the estimator block is further arranged for determining the estimated control signal by performing a truncation on the outcome of said multiplying. Advantageously the all-digital phase-locked loop comprises scaling means for scaling the estimated control signal before performing the truncation.
In another preferred embodiment the estimator block is further arranged for performing clamping on the estimated control signal.
In another embodiment said multiplying is with a power of the absolute value instead of the absolute value itself.
In an embodiment the all-digital phase locked loop further comprises a digital loop filter arranged for receiving the fractional phase error and an integer phase error obtained by computing the difference between the integer part and a variable phase signal.
In yet another embodiment the all-digital phase locked loop further comprises a digital clock oscillator connected to the digital loop filter and arranged for outputting the desired clock signal phase.
In another aspect the invention relates to a method for calibrating a time-to-digital converter in an all-digital Phase-Locked Loop, said all-digital Phase-Locked Loop comprising a reference phase generator to which a digital signal is fed and split into an integer part and a fractional part, an estimator block estimating a control signal, a digital-to-time converter which receives said estimated control signal and a reference clock signal and derives a delayed reference clock signal using said reference clock signal and said estimated control signal, said time-to-digital converter receiving said delayed reference clock signal and a desired clock signal phase and for deriving a fractional phase error, wherein said estimator block receives also said fractional phase error and determines said estimated control signal by
For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
The above and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.
The invention will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims.
Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.
It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.
In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
As already mentioned, all digital phase locked loops are a low power alternative in modern CMOS technologies. However, due to PVT variations the AD-PLL needs to be calibrated, especially the delay line elements in the feedback path of the AD-PLL. Prior art delay line calibration algorithms fail for small fractional settings in the relation between the RF clock and the reference crystal. Moreover, for conventional settings they require a settling time which is too long for many standards. The present invention presents a solution to these issues.
Basically the invention proposes the use of more information, such that significant control signals are passed when a phase error measurement is reliable. To improve convergence and stability, the solution space of the calibration loop is preconditioned by applying the second norm. In a fixed point implementation the bit words are rounded such that small disturbances are neglected in the loop, as they have no real control information. More technical details are provided in the rest of this description.
An advantageous embodiment is illustrated in
Another advantage of this embodiment is that a rounding function is included at the output of the second norm. The rounding function is provided by a truncation block 440 which removes some of the LSB bits of the digital signal at the output of the second norm block 420. For example, the LSBs which are not distinguishable from signals caused by noise can be removed. This rounding thus offers the benefit that small control signals caused by noise or small disturbances are ignored. This means the estimation is more stable when settled. The rounding function of block 440 can be seen as a quantization function.
Another embodiment is shown in
In yet another embodiment it is possible to use higher norms than the second norm. However, simulations indicate there is virtually no benefit of using a higher norm.
In another embodiment the rounding at the output of the second norm can also be shifted to the input of the second norm, which allows for less costly implementation of the second norm block.
The PHE_F signal can be sign bit only or may contain all or some of the bits for the embodiments of
In order to illustrate the beneficial effect of the proposed solution some simulation results are now presented. In
In
In
In
One can observe in
In the TDC design the presence of a zero fractional phase error has been omitted. Therefore the TDC output is always early or late, even when K_dtc is estimated perfectly. Since there always is early late toggling, this introduces continuous control to the K_dtc estimation algorithm. To have better behaviour after settling, the rounding is chosen to be such that this early late toggling is mostly ignored.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. The invention is not limited to the disclosed embodiments.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope.
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一种应用于全数字锁相环的数字控制振荡器 | 2020-05-15 | 675 |
一种基于全数字锁相环的高精度同步时钟实现方法 | 2020-05-23 | 410 |
全数字锁相环及其控制方法 | 2020-05-25 | 428 |
时间数字转换器、全数字锁相环电路及方法 | 2020-05-24 | 100 |
相位锁定检测输出电路及全数字锁相环系统 | 2020-05-14 | 190 |
可变相位累加器电路结构的全数字锁相环及锁相控制方法 | 2020-05-15 | 949 |
数控振荡器和基于数控振荡器的全数字锁频环和锁相环 | 2020-05-20 | 742 |
CMOS相位插值数控振荡器 | 2020-05-20 | 810 |
ALL DIGITAL PHASE LOCKED LOOP | 2020-05-22 | 982 |
60 GHZ FREQUENCY GENERATOR INCORPORATING THIRD HARMONIC BOOST AND EXTRACTION | 2020-05-25 | 973 |
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