| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 101 | JPS6313605B2 - | JP17837280 | 1980-12-17 | JPS6313605B2 | 1988-03-26 | FUJITA KENGO; MATSUDA KIICHI; PPONMA TOSHIHIRO; FUKUDA YUTAKA |
| 102 | JPS6016141B2 - | JP4662175 | 1975-04-18 | JPS6016141B2 | 1985-04-24 | RARUFU KAATAA BUREINAADO; JEEMUSU CHAARUZU KYANDEI |
| 103 | Differential pcm coder or decoder | JP16796582 | 1982-09-27 | JPS5957539A | 1984-04-03 | AKAGIRI KENZOU; NISHIGUCHI MASAYUKI |
| PURPOSE:To reduce the feeling of distortion when a high frequency band signal is included in transmitting a sound signal, by transmitting a signal in the differential PCM system with the input state having less high frequency signal component, and transmitting it in the linear PCM system as the high frequency component is increased. CONSTITUTION:An input signal is applied to a terminal 1 of a coder, and converted into a PCM signal at A/D converters 2 and 3. An output of the converter 3 is delayed by a sampling section at a 1-bit delay device 5, subtracted from the output of the converter 2 at a subtractor 4, and the result is transmitted from a terminal 6 as the PCM signal. Further, a coded digital signal is fed to a terminal 10. This signal is converted at an A/D converter 12 and converted again into the digital signal at an A/D converter 13 and added 11 to the input digital signal. One-bit delay is produced at the converter 13, a difference value transmitted to the sampling value before one sampling section is added at an adder 10 and the original analog signal is decoded from an output terminal 14. | ||||||
| 104 | Generating circuit for differential pulse code modulation signal | JP17837280 | 1980-12-17 | JPS57101421A | 1982-06-24 | FUJITA KENGO; MATSUDA KIICHI; HONMA TOSHIHIRO; FUKUDA YUTAKA |
| PURPOSE:To decrease an operating time, by omitting a weighting circuit provided at a transmission circuit from an output terminal of a forecast circuit to an input terminal of a differential device. CONSTITUTION:A sampling signal incoming to an input terminal 8 is applied to a weighting circuit 9, where the signal is multiplied with a 1/alpha which is a reciprocal of a leakage coefficient alpha of a weighting circuit 14, and the signal is applied to a differential device 10. The differential device 10 obtains a differential signal by subtracting a forecast signal from a forecast circuit 13 from the sampling signal multiplied with 1/alpha, and the differential signal is applied to a quantization circuit 11. The quantization circuit 11 produces a DPCM signal by PCM encoding of a signal multiplied by alpha for the differential signal and outputs it to an output terminal 15 and an adder 12 respectively. The adder 12 adds the DPCM signal and a signal obtained by multiplying the output forecast signal of the forecast circuit by alpha at the weighting circuit 14 and supplies it to the forecast circuit 13. | ||||||
| 105 | JPS5714070B2 - | JP8609072 | 1972-08-28 | JPS5714070B2 | 1982-03-20 | |
| 106 | JPS56500920A - | JP50184880 | 1980-06-18 | JPS56500920A | 1981-07-09 | |
| 107 | Waveform coder | JP6714777 | 1977-06-06 | JPS54914A | 1979-01-06 | FUSHIKIDA KATSUNOBU |
| PURPOSE:To reduce the amount of operation without deteriorating S/N, by performing optimized coding only for the quantized level near the code series based on the code series from a coder, in DPCM system. | ||||||
| 108 | JPS4832419A - | JP8609072 | 1972-08-28 | JPS4832419A | 1973-04-28 | |
| 109 | JPS6345129B2 - | JP50184880 | 1980-06-18 | JPS6345129B2 | 1988-09-08 | AAPUFUERU RATSUSERU JEI; ERIKUSOON ANDAASU GUNNAA; SUBENSOON RAASU TOMII EDOWAADO |
| 110 | Differential pcm signal generating circuit | JP19940586 | 1986-08-26 | JPS6354827A | 1988-03-09 | ABE MIKI |
| PURPOSE: To obtain the bit compression effect over a wide band by applying over-sampling to an input PCM data whose sampling frequency is fs so as to generate a PCM data having the sampling frequency of nfs (n is an integral number being ≥2) and applying signal processing to said PCM data to obtain a differential PCM data. CONSTITUTION: The titled circuit is provided with a digital filter 1 applying over-sampling to the input PCM data whose sampling frequency is fs so as to generate the PCM data of the sampling frequency nfs(n is an integral number being ≥2) and a signal processing means 2 applying signal processing to the PCM data whose sampling frequency is nfs to obtain the differential PCM data. In the filter 1, the input PCM data having the sampling frequency fs is subjected to over-sampling to generate the PCM data of the sampling frequency nfs. Then the result is fed to a subtraction circuit 2, where the PCM data before one sampling period from the present PCM data is subtracted to obtain the differential PCM data. Thus, the bit compression effect by the difference PCM is obtained over a wide range. COPYRIGHT: (C)1988,JPO&Japio | ||||||
| 111 | JPS6248410B2 - | JP18969281 | 1981-11-26 | JPS6248410B2 | 1987-10-14 | TANAKA HIDEFUMI; KIUCHI TSUTOMU |
| 112 | JPS61500943A - | JP50024285 | 1984-12-08 | JPS61500943A | 1986-05-08 | |
| PCT No. PCT/DE84/00267 Sec. 371 Date Sep. 3, 1985 Sec. 102(e) Date Sep. 3, 1985 PCT Filed Dec. 8, 1984 PCT Pub. No. WO85/03177 PCT Pub. Date Jul. 18, 1985.A differential pulse code modulation system wherein digital code words assigned to the signal differences adjacent to the signal difference "Zero" have the same number of bits of one or the other logical level. In this manner, "d.c. voltage" information in the transmitted signal is neutralized. | ||||||
| 113 | JPS6013342B2 - | JP6825276 | 1976-06-12 | JPS6013342B2 | 1985-04-06 | MARINASU KOONERISU UIREMU FUAN BUURU |
| 114 | Signal interpolating method of decoding circuit of dpcm-coded signal processing circuit | JP19304682 | 1982-11-02 | JPS5981918A | 1984-05-11 | KAMIYA KENJI; SHIAKU YOSHIYUKI |
| PURPOSE:To perform excellent DPCM encoding with the minimum usage of memory by chopping a component of a differential analog signal in every decoding period at plural points by a chop control signal, and performing integration plural times in every decoding period. CONSTITUTION:A differential digital signal outputted from a digital processing circuit 4 is converted by a D/A converting element 7 into a differential analog signal, which is sent to a gate 10 consisting of an analog switch. An interpolating pulse generating circuit 9, on the other hand, generates an interpolating pulse signal on the basis of a clock signal from a master clock circuit 5 so that two pulse signals are positioned at a stable intermediate part in a signal in one stepwise decoding period of the differential analog signal, thereby outputting it to the gate 10 as the chop control signal. When the chop control signal with a high level is applied to the gate 10, the gate 10 extracts the intermediate part of the differential analog signal in each period as a difference signal with a quantization level intermittently twice each and sends it to an integrator 8. | ||||||
| 115 | Decoding circuit of differential pulse code modulation | JP7776882 | 1982-05-10 | JPS58195332A | 1983-11-14 | HASHIZUME MASAO |
| PURPOSE:To eliminate erroneous components in a short time, by providing an HPF designating the lower limit of a reproduced frequency band as a cutoff frequency to the post-stage of a D/A converter and giving the HPF an analog signal of an adding output between a DPCM input and the preceding prediction signal. CONSTITUTION:The HPF 4 takes the lower limit frequency f0 of a reproduced frequency band as the cutoff frequency and eliminates erroneous signal components included in the adding output. In an output signal of a D/A converter 3, the erroneous signal component is attenuated by the HPF4 as shown in a figure DS and erased after 1/f0. The analog signal in which the erroneous component is attenuated and eliminated is converted into a digital signal by an A/D converter 6, stored in a memory 1 sequentially as a prediction signal and applied to a signal processing section. Thus, a signal in which the erroneous component is eliminated after 1/f0 is outputted from an LPF5 as shown in a figure ES. | ||||||
| 116 | Analog-to-digital converter | JP18969281 | 1981-11-26 | JPS5890844A | 1983-05-30 | TANAKA HIDEFUMI; KIUCHI TSUTOMU |
| PURPOSE:To decrease the period of malfunction even with mixed error signals, by increasing the utilizing efficiency of encoded bit number and reducing the amount of data, through the differential pulse code modulation of a modulated wave signals angular-modulated with an analog signal. CONSTITUTION:An analog input signal ei is applied to a frequency modulator 10 for frequency modulation. A modulated wave signal eFM is applied to a low pass filter 11 in which high frequencies are attenuated in the rate of -6dB/oct, and an output e'FM is applied to a subtractor 2. An output eD=e'FM-e0 of the subtractor 2 is applied to an encoder 3 for encoding to obtain a digital signal ED. The digital signal ED is applied to a digital integrator consisting of an adder 4 and a latch 6 to generate an estimation signal E1. This estimation signal E1 is applied to a decoder 9 via a latch 8, where the signal is converted into an analog estimation signal e0 and applied to the subtractor 2. | ||||||
| 117 | Data compression device using finite difference | JP17415681 | 1981-10-29 | JPS5875341A | 1983-05-07 | MIYAZAKI HIROSHI |
| PURPOSE:To perform the data compression with no reduction of the S/N regardless of a decreased mean data length, by expressing the finite difference value of the great number of times of appearance with a small data length and the finite difference value of the small number of times of appearance with a large data length respectively. CONSTITUTION:For a differential coder, the sampled input signal is turned into a finite difference value with subtraction given to the previous process value through a subtracting part 1 and quantized at a quantizing part 2 and also coded at a coding part 3 to be transmitted or stored in the form of a coding data. On the other hand, a differential demodulator decodes the input coding data to a finite difference value through a decoding part 6. This finite difference value is added with the previous value through an adding part 7 to be used as the present value. This present value is delivered in the form of signals. The present value is held for a sampling period at a delaying part 8 and then set equal to the previous value due to the finite difference value of the next coding data. | ||||||
| 118 | Method of encoding analog signal | JP2914282 | 1982-02-26 | JPS57159144A | 1982-10-01 | BIERUN BURIYUUTOGEN |
| 119 | JPS5726453B2 - | JP3332176 | 1976-03-26 | JPS5726453B2 | 1982-06-04 | |
| 120 | JPS57500858A - | JP50184881 | 1980-06-18 | JPS57500858A | 1982-05-13 | |
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