| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | Differential pulse code modulator system with cyclic, dynamic decision level changing | US3699446D | 1970-12-24 | US3699446A | 1972-10-17 | SAINTE-BEUVE PHILIPPE |
| A device for the transmission of an information signal by means of pulse code modulation features a quantizing circuit controlled by a control circuit so that the decision levels of the quantizing circuit are cyclically changed between predetermined minimum and maximum values.
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| 22 | Reversible analog-digital converter utilizing incremental discharge of series connected charge sharing capacitors | US3449741D | 1965-02-08 | US3449741A | 1969-06-10 | EGERTON MCKENNY W JR |
| 23 | Dual code differential encoding scheme for video signals | US3422227D | 1965-09-30 | US3422227A | 1969-01-14 | BROWN EARL F |
| 24 | Predictive quantization and coding of vision signals | US6452460 | 1960-10-24 | US3090008A | 1963-05-14 | MOUNTS FRANK W |
| 25 | Signal predicting apparatus | US17097850 | 1950-06-29 | US2701274A | 1955-02-01 | OLIVER BERNARD M |
| 26 | 차동 비선형 오류 보정용 아날로그 디지털 컨버터 | KR1020040077910 | 2004-09-30 | KR1020060028971A | 2006-04-04 | 김미경 |
| 본 발명은 차동 비선형 오류 보정용 아날로그 디지털 컨버터에 관한 것으로서, 보다 상세하게는 기준전압 발생부에 저항보정회로를 구비하여 저항 미스매치에 의한 차동 비선형(differential non-linearity; DNL) 오류를 보정하여 아날로그 디지털 컨버터의 오류를 방지하는 기술이다. 이를 위해, 본 발명은 아날로그 입력신호와 기준전압신호를 비교하는 비교부와, 상기 비교부의 출력을 순차적으로 저장하는 레지스터와, 상기 레지스터에 저장된 디지털 코드값이 정상인지 여부를 판단하고 그 결과에 따라 저항값을 보정하여 상기 기준전압신호를 출력하는 기준전압 발생부를 포함하여 구성함을 특징으로 한다. | ||||||
| 27 | 보간 에널로그 디지틀 변환기 | KR1019810001701 | 1981-05-18 | KR1019870001097B1 | 1987-06-04 | 류우셀제이압펠; 안더어스건너어엘릭손; 라아스토오미에드워드세븐선 |
| The interpolative A-D converter for telecommunications subscriber line incorporated with digital filtering has an integrator for the difference between an input analog signal and a quantised signal. A first comparator samples the intergrating signal at a first sampling frequency. A second comparator receives the input signal and the quantised signal and samples the results of the comparision at the first frequency to develop second signals of one data state when the input signal is greater than the quantised signal and does the results of another data state when the input signal is less than the quantised signal. | ||||||
| 28 | 낸드 게이트와 소스 증폭기를 이용한 차동 스위치 구동회로 | KR1020090104020 | 2009-10-30 | KR1020110047406A | 2011-05-09 | 윤광섭; 황정진 |
| PURPOSE: A differential switch circuit using an NAND gate and a source amplifier is provided to reduce the over-drive voltage by reducing a swing width of a digital signal applied to a differential switch. CONSTITUTION: A current generating unit(100) is connected to a first common node(CN1) to receive uniform static current. A differential switch unit(300) is connected to the current generating unit through a first common node, and supplies uniform static current. A switch driving circuit unit(500) includes a first source amplifier(510) connected to a third NMOS transistor, a second source amplifier(530) connected to a fourth NMOS transistor, and a NAND gate connected to the first and second source amplifiers. | ||||||
| 29 | 보간 에널로그 디지틀 변환기 | KR1019810001701 | 1981-05-18 | KR1019830006997A | 1983-10-12 | 류우셀제이압펠; 안더어스건너어엘릭손; 라아스토오미에드워드세븐선 |
| 내용없음 | ||||||
| 30 | DIGITAL TO ANALOGUE CONVERSION | US15577637 | 2016-05-26 | US20180167081A1 | 2018-06-14 | John Robert Stuart |
| Devices and methods for digital to analogue conversion (DAC) are provided, in which the analogue outputs of an even number of digital to analogue converters are combined. The individual converters operate on the same data but there is a relative time delay between the input digital signal received by one or more of the converters and the input digital signal received by other of the converters, wherein the delay is a fraction of the data sample period. Moreover, the data signal fed to half of the converters has an inverse relationship with the data signal fed to the other half of the converters and their analogue outputs are subtracted. Dither and filtering techniques may also be employed. | ||||||
| 31 | Sensor circuit | US15244368 | 2016-08-23 | US09897635B2 | 2018-02-20 | Edwin Schapendonk |
| A sensor circuit incorporates an analog to digital converter for providing a digital signal derived from sensing elements connected in a bridge configuration. The sensor circuit comprises first and second paths comprising respective first and second sensing elements connected between first and second supply lines; an analog to digital converter having a differential input connected to receive a differential voltage signal (Vinp−Vinn) between the first and second sensing elements and an output for providing a digital output signal (Dout) representing a difference between the first and second sensing elements, the analog to digital converter comprising: current sources connected between the first and second supply lines, each current source being switchably connected to either the first or second sensing elements; and control logic configured to selectively switch current from each of the current sources to either the first path or the second path in dependence on the differential voltage signal. | ||||||
| 32 | SENSOR CIRCUIT | US15244368 | 2016-08-23 | US20170131333A1 | 2017-05-11 | Edwin Schapendonk |
| A sensor circuit incorporates an analogue to digital converter for providing a digital signal derived from sensing elements connected in a bridge configuration. The sensor circuit comprises first and second paths comprising respective first and second sensing elements connected between first and second supply lines; an analogue to digital converter having a differential input connected to receive a differential voltage signal (Vinp-Vinn) between the first and second sensing elements and an output for providing a digital output signal (Dout) representing a difference between the first and second sensing elements, the analogue to digital converter comprising: current sources connected between the first and second supply lines, each current source being switchably connected to either the first or second sensing elements; and control logic configured to selectively switch current from each of the current sources to either the first path or the second path in dependence on the differential voltage signal. | ||||||
| 33 | Analog-to-digital conversion loop for PS15 and WSS systems | US13926455 | 2013-06-25 | US08872682B2 | 2014-10-28 | Vanni Poletto; Carlo Antonini; Salvatore Cannavacciuolo |
| An analog-to-digital conversion loop adapted to generate a digital output signal corresponding to a low-pass filtered replica of an analog input signal, including an analog adder configured to receive the input analog signal and an analog feedback signal, adapted to generate an analog error signal corresponding to the difference between the analog input signal and the analog feedback signal; an analog-to-digital converter having a nonlinear input-output conversion characteristic defining a larger quantization step the more the input to be converted differs from a null value, configured to receive the analog error signal and to generate a corresponding digital error signal a digital integrator configured to receive the digital error signal, configured to generate the digital output signal corresponding to the time integration of the digital error signal; a digital-to-analog converter, configured to receive the digital output signal and to generate the analog feedback signal as analog replica of the digital output signal. | ||||||
| 34 | A/D converter and solid-state imaging device | US12872417 | 2010-08-31 | US08174427B2 | 2012-05-08 | Hiroshi Mashiyama; Satoshi Akabane |
| According to one embodiment, an A/D converter includes a determination circuit configured to determine whether a first analog signal is greater than a second analog signal or not, the first analog signal being a present A/D conversion target, the second analog signal being an immediately preceding A/D conversion target, a calculation circuit configured to add a reference voltage to a difference obtained by subtracting the second analog signal from the first analog signal, a generation circuit configured to generate a comparison voltage, a comparator configured to compare a calculated value of the calculation circuit with the comparison voltage, and a conversion circuit configured to convert a period into a digital signal, the period being required until the calculated value is identical with the comparison voltage by the comparator. | ||||||
| 35 | Differential pulse code modulation system with neutralization of direct current information | US775511 | 1985-09-03 | US4792794A | 1988-12-20 | J/u/ rgen Heitmann |
| A differential pulse code modulation system wherein digital code words assigned to the signal differences adjacent to the signal difference "Zero" have the same number of bits of one or the other logical level. In this manner, "d.c. voltage" information in the transmitted signal is neutralized. | ||||||
| 36 | Method for encoding analog signals | US343811 | 1982-01-29 | US4453158A | 1984-06-05 | Bjoern Bluethgen |
| A method for encoding analog signals for storage or transmission includes the steps of sampling momentary values of the analog signals and converting the sampled values into PCM code words and forming PCM differential code words from two successive PCM words, each of the differential PCM words being of a prescribed length. The length of the generated differential PCM words are continuously compared to a reference code word and upon the length of a differential code word exceeding a specified length the word is either abbreviated by a companded differential PCM word by eliminating some of the least significant code elements, or by division of the excess-length word into two successive code words respectively comprising the least significant and most significant bits of the excess-length word, the differential PCM words additionally being replaced by PCM words when the associated signal content does not exceed the length prescribed by the reference code word. | ||||||
| 37 | Method for encoding analog signals using PCM difference code word for forming a code word of specified length | US189595 | 1980-09-22 | US4438522A | 1984-03-20 | Bjoern Bluethgen |
| A method for encoding analog signals for storage or transmission purposes, particularly for the digital recording of audio signals in studio devices, samples periodic values of the analog signals and converts the sampled values into pulse-code modulation code words. Successive pulse-code modulation code words are transformed by means of subtraction into pulse-code modulation difference code words and, together with additional auxiliary code elements, form a reference code word having a selected constant length. A reduction of the digital signal flow is achieved as a result of the reference code word, including the auxiliary code elements, being selected shorter than the maximum possible length of a pulse-code modulation difference code word. The generated pulse-code modulation difference code words are continuously monitored as to length, and upon the identification of a difference code word having an excess length, that is, greater than the reference code word, either the excess-length difference code word is abbreviated or is replaced by a pulse-code modulation code word of suitable length. | ||||||
| 38 | Multistage selective differential pulse code modulation system | US928372 | 1978-07-27 | US4229820A | 1980-10-21 | Hajime Enomoto |
| A differential pulse code modulation system, in which an input signal is at first approximated to a stepwise waveform having level changes at a constant number n of sampling points selected in the order of level magnitude from a predetermined number N of samples in the input signal. The remainder of the above approximating operation is secondary followed-up by delta modulation, which uses a variable step level controlled in accordance with the variation feature of the remainder. The differential pulse code modulation output is provided by the above two approximating operations. | ||||||
| 39 | US26228772 | 1972-06-13 | USB262287I5 | 1975-01-28 | ||
| 40 | Pulse code modulation system | US3657653D | 1970-04-27 | US3657653A | 1972-04-18 | WILKINSON ROGER MARTIN |
| A pulse code telecommunications system in which samples of an analogue signal to be transmitted are each represented by a binary word. In each binary word, one signal bit represents the polarity of the sample with respect to a reference level and one or more further signal bits represent the magnitude of the sample with respect to a second, variable, reference level which is derived from the coded representation of the magnitudes of preceding samples. The system includes a binary signal multiplexer and a transmitter. A receiver for use with the system includes a binary signal demultiplexer, circuits for correctly allocating the polarity and magnitude bit signals to polarity and magnitude signal channels, and decoder circuits for reconstituting the analogue signal from the binary word signal.
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