| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 81 | Mobile imaging applications, equipment, architecture and service platform architecture | JP2007536967 | 2005-10-12 | JP2008516565A | 2008-05-15 | ディー コラロフ クラシミル; ディー ラルストン ジョン; イー サンダース スティーヴン |
| 移動装置の静止画像及びビデオ画像データを圧縮し及び圧縮解除する装置及び方法を提供する。 対応する移動装置アーキテクチャ、無線及び有線ネットワーク上の静止画像及びビデオ画像を送信し、記憶し、編集し及びトランスコードするとともに静止画像及びビデオ画像が表示可能な装置で見られるサービスプラットホームアーキテクチャも提供する。 | ||||||
| 82 | Signal, a storage medium, a method for encoding and an apparatus, a method for decoding and equipment | JP2003585300 | 2003-04-17 | JP2005523601A | 2005-08-04 | アントニウス アー ツェー エム カルケル; ウィレム エム ヨット エム ケーネ |
| 【課題】チャンネルサイド情報を使用する必要性が、回避される、または少なくとも、かなり減ぜられる、エラー位置のための代替方法を提供すること。
【解決手段】 本発明は、ランレングス・リミテッド(RLL)符号化されたバイナリ d , kチャンネル・ビットストリームを有する信号であって、パラメータ dが、当該ビットストリーム3の任意の2つの「1」の間の「0」の最小数を定義し、かつパラメータ kが、最大数を定義し、またはその逆を定義し、RLL行8〜13、45と呼ばれる、それぞれ N個の逐次的RLLチャネルビットの多数のセクションを有し、各RLL行8〜13、45が、当該RLL行8〜13、45に対するいわゆる行ベースのパリティチェック制約が実現された、行パリティチェック・コードワードと呼ばれるパリティチェック・コードワードを表す、信号において、 M個のRLL行8〜13、45のグループの予め定められた位置で、列パリティチェック行21、 22、 43、 44、46と呼ばれる、それぞれ N個の逐次的チャネルビットの K個のセクションが、位置づけられることを特徴とし、 K 、 Nおよび Mが、整数値であり、当該列パリティチェック行21、 22、 43、 44、46が、複数の列パリティチェック使用可能なチャンネルワード30, 42, 48を有し、当該列パリティチェック使用可能なチャンネルワード30, 42, 48の各々が、特定の列パリティチェック使用可能なチャンネルワード30, 42, 48に対応する当該グループの少なくとも当該 M個のRLL行8〜13、45の全てのいわゆる対応するセグメントに対して、いわゆる列ベースのパリティチェック制約を実現させ、これによって、列パリティチェック・コードワードを構成する。 さらに、本発明は、このような信号を有する記憶媒体、並びにユーザ・データビットのストリームをこのような信号に符号化する方法および装置、並びに、このような信号を復号化する方法および装置に関する。 |
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| 83 | METHOD FOR QUANTIZING INPUT SIGNAL OF N SAMPLES INTO STRING OF k SYMBOLS DRAWN FROM q-ARY ALPHABET | JP2004277703 | 2004-09-24 | JP2005110251A | 2005-04-21 | YEDIDIA JONATHAN S; MARTINIAN EMIN |
| <P>PROBLEM TO BE SOLVED: To provide a method for quantizing an input signal of N samples into a string of (k) symbols drawn from a q-ary alphabet. <P>SOLUTION: A complementary method reproduces a minimally distorted version of the input signal from the quantized string, given some distortion measure. First, an [N, k]<SB>q</SB>linear error-correcting code that has a sparse generator factor graph representation is selected. A fixed mapping from q-ary symbols to samples is selected. A soft-input decoder and an encoder for the SGFG codes are selected. A cost function is determined from the input signal and a distortion measure, using the fixed mapping. The decoder determines an information block corresponding to a code word of the SGFG code with a low cost for the input signal. The input signal can be reproduced using the encoder for the SGFG code, in combination with the fixed mapping. <P>COPYRIGHT: (C)2005,JPO&NCIPI | ||||||
| 84 | Valid data and redundant data channel decoding method and channel decoding apparatus of a data stream having the computer readable storage medium, a computer program element | JP2001577706 | 2001-04-11 | JP2003531550A | 2003-10-21 | ベーゼ ゲーロ; ブルケルト フランク; ブッシュマン ラルフ |
| (57)【要約】 データストリームは有効データと冗長データとエラーを含む少なくとも１つのソース符号化ビットシーケンスとを有しており、このビットシーケンスはデータストリーム内の所定の位置をマーキングしている。 エラーのないソース符号化ビットシーケンスはチャネル復号器で既知である。 データストリームはまずチャネル復号化され、エラーを含むソース符号化ビットシーケンスを考慮してもう一度チャネル復号化される。 | ||||||
| 85 | Coder, method therefor and serving medium | JP21835099 | 1999-08-02 | JP2001044856A | 2001-02-16 | MURAYAMA ATSUSHI; MIYAUCHI TOSHIYUKI; HATTORI MASAYUKI |
| PROBLEM TO BE SOLVED: To map a code on one transmission symbol. SOLUTION: A convolution coder 201 for external codes applies convolution arithmetic operation to received data at a coding rate of 2/3 and outputs the result of the arithmetic operation to an interleaver 202. The interleaver 202 interleaves date received from the convolution coder 201 and outputs the result to a convolution coder 203. The convolution coder 203 for inner codes applies convolution arithmetic operation to the data from the interleaver 202, at a coding rate of 1(=3/3) and outputs the result of arithmetic operation to a multi- valued modulation mapping circuit 204. The multi-valued modulation mapping circuit 204 maps the data received from the convolution coder 203 to the transmission symbol of an 8PSK modulation system. | ||||||
| 86 | Information bit sequence transmitting process | JP30292896 | 1996-11-14 | JPH1028060A | 1998-01-27 | LASNE XAVIER |
| PROBLEM TO BE SOLVED: To obtain a process which can protect a bit to be transmitted from an error introduced from a transmission channel. SOLUTION: An encoder form a second sequence of bits Cn containing a redundant subset based on a sequence of information bits to be transmitted and generates a third sequence of bits dn by performing differential encoding in the form of an exclusive OR operation between the bits Cn and f(n) (f(n)<n). Transmitting signals obtain likelihood data rn related to the bits dn and a receiver calculates the estimated value of the bits of the redundant subset as the function of rn and rf(n) , detects the bit Cn of a subset having an erroneous estimated value by utilizing the redundancy, and corrects the less-reliable codes of two related likelihood data items rn and rf(n) . | ||||||
| 87 | Transmitter, receiver and decoder | JP13583993 | 1993-06-07 | JPH06204985A | 1994-07-22 | GERUTO TSUINMAAMAN; YURUGEN PEETAASEN |
| PURPOSE: To detect a transmission error and effectively correct it by transmitting a digital signal, without reducing a valid data rate. CONSTITUTION: A deciding circuit 4, a 2nd diciding unit 42 for estimating the bit error rate of decoded information signal 3 and/or 3rd deciding unit 43 for detecting a 3rd error signal e3 for synchronizing the digital signal are provided. These decision units respectively evaluate a sum S, formed from binary values W1...WM in a memory means SR. | ||||||
| 88 | METHOD AND APPARATUS OF JOINT SECURITY ADVANCED LDPC CRYPTCODING | EP15818263 | 2015-07-10 | EP3167566A4 | 2018-03-14 | PISEK ERAN; ABU SURRA SHADI |
| A JSALE encoder includes a first encryption layer to apply a first encryption key to a plaintext input data. The JSALE encoder includes a row encoding module to: generate parity bits of a current layer of an H-matrix by applying a LDPC encoding process to the encrypted input data, and generate a cryptcoded data appending the parity bits to the encrypted input data. The JSALE encoder includes a second encryption layer to initiate each subsequent round of the JSALE process through round Nr and to output a ciphertext after the Nr round. | ||||||
| 89 | SOFT GENERATION OF BIOMETRIC CANDIDATES AND REFERENCES BASED ON BASED ON EMPIRICAL BIT ERROR PROBABILITY | EP15710189.0 | 2015-03-17 | EP3120285B1 | 2017-10-25 | LINNARTZ, Johan-Paul Marie Gerard |
| A biometric verification device (100) arranged to compare a reference hash (480) with a verification bit string (420) obtained from a biometric, the biometric verification device comprising: —a candidate bit string generator (130) arranged to generate candidate bit strings (430) from the verification bit string and error probabilities, —a hash unit (140) arranged to apply a cryptographic hash function to said generated candidate bit strings to obtain candidate hashes, —a comparison unit (160) arranged to verify if a candidate hash generated by the hash unit matches a reference hash. | ||||||
| 90 | MULTI-WIRE SYMBOL TRANSITION CLOCKING SYMBOL ERROR CORRECTION | EP15805713.3 | 2015-11-24 | EP3224977A1 | 2017-10-04 | SENGOKU, Shoichiro |
| Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver. | ||||||
| 91 | INFORMATION DETECTION METHOD AND APPARATUS FOR HIGH SPEED DOWNLINK SHARED CONTROL CHANNEL | EP10791222.2 | 2010-04-13 | EP2439976B1 | 2016-04-13 | XIAO, Haiyong |
| 92 | Detection and decoding in flash memories with selective binary and non-binary decoding | EP14153544.3 | 2014-01-31 | EP2763042B1 | 2015-09-09 | Alhussien, Abdel Hakim S.; Li, Zongwang; Haratsch, Erich F.; Danjean, Ludovic |
| 93 | METHOD AND APPARATUS FOR DECODING RECEIVED DATA SIGNALS | EP08751147.3 | 2008-02-11 | EP2243240B1 | 2015-08-26 | VILLION, Mathieu; POIRIER-CLARAC, Laurence; TARDY, Pierre |
| 94 | RECEIVER, TRANSMITTER, AND COMMUNICATION METHOD | EP13832457.9 | 2013-08-27 | EP2892158A1 | 2015-07-08 | MATSUMOTO, Wataru; AKINO, Toshiaki; MIYATA, Yoshikuni; SUGIHARA, Kenya; SUGIHARA, Takashi; FUJIMORI, Takafumi |
A receiver, a transmitter, and a communication method, which exhibit performance close to that of synchronous detection even when a phase slip occurs, are obtained. Provided are a transmitter (10) for transmitting a transmission signal subjected to modulation after error correction coding and a receiver (20) including a phase compensation unit (21, 22) for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit (23 to 25) for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data. |
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| 95 | AES IMPLEMENTATION WITH ERROR CORRECTION | EP13713845.9 | 2013-03-27 | EP2885892A1 | 2015-06-24 | EFTEKHARI, Yaser; WIENER, Michael; ZHOU, Yongxin |
| A method of cryptographically processing a block of data, the method comprising: receiving an encoded version of the block of data, wherein the encoded version of the block of data comprises the block of data encoded, at least in part, using an error control code; and processing the encoded version of the block of data using a predetermined function to generate an output, wherein the predetermined function is arranged so that the result of processing, with the predetermined function, a quantity of data encoded, at least in part, using the error control code equals the result of encoding, at least in part, with the error control code the result of performing encryption or decryption of the quantity of data according to the Advanced Encryption Standard, AES. | ||||||
| 96 | APPARATUS FOR ADAPTABLE/VARIABLE TYPE MODULATION AND DEMODULATION IN DIGITAL TX/RX SYSTEM | EP09766809 | 2009-06-16 | EP2317657A4 | 2015-06-03 | KIM SUNG-HOON; LEE EUNG DON; CHOI JIN SOO; HONG JIN WOO; AHN CHUNG HYUN; KIM CHANG-JOONG; LEE KYOUNG-HWEON; LEE HO-KYOUNG |
| 97 | INFORMATION DETECTION METHOD AND APPARATUS FOR HIGH SPEED DOWNLINK SHARED CONTROL CHANNEL | EP10791222 | 2010-04-13 | EP2439976A4 | 2015-02-11 | XIAO HAIYONG |
| 98 | FORWARD ERROR CORRECTION CODING/DECODING METHOD, DEVICE AND SYSTEM | EP11878400 | 2011-12-30 | EP2790327A4 | 2014-12-24 | CHANG DEYUAN; YU FAN; XIAO ZHIYU |
| 99 | Method and system for providing low density parity check (ldpc) coding for scrambled coded multiple access (SCMA) | EP11150777.8 | 2011-01-12 | EP2343810A2 | 2011-07-13 | Lee, Lin-Nan; Eroz, Mustafa |
A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.
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| 100 | COLLUSION RESISTANT WATERMARKING GENERATION METHOD | EP08876352.9 | 2008-09-26 | EP2327054A1 | 2011-06-01 | LIN, Wan-yi; BLOOM, Jeffrey, Adam; HE, Shan |
| A method and system of detecting colluders conducting a collusion attack including a minority-type collusion attack on a digital product includes the generation of codewords used as watermarks in the digital product. The inner code of the codewords is generated using permutations of rows in a Hadamard matrix and concatenating them together. A typical outer code of the codeword is the Reed Solomon code. An adaptive detector is able to accurately detect one of three or more colluders of a minority-type attack. Prior art schemes using an error correcting code-based watermarking mechanism with an inner code fail to detect colluders with a minority-type collusion attack which includes three colluders. | ||||||
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