| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Information detection method and apparatus for high speed downlink shared control channel | US13258393 | 2010-04-13 | US08526312B2 | 2013-09-03 | Haiyong Xiao |
| An information detection method and apparatus for a High Speed Downlink Shared Control Channel (HS-SCCH) are provided by the present disclosure, implementing the detection of HS-SCCH part1 with low false alarm probability and low false dismissal probability under the arbitrary combination of User Identifiers (UEID). The method is that: rate de-matching the front detection signal of each HS-SCCH part1 in the terminal HS-SCCH monitor set, obtaining the corresponding rate de-matched information; removing the user mask for the rate de-matched information of each HS-SCCH monitor channel; Viterbi decoding each rate de-matched information of which the user mask is removed, obtaining Viterbi-decoding 0 state accumulated metric of each HS-SCCH in HS-SCCH monitor set, and summing the absolute value of the soft information of each HS-SCCH monitor channel respectively, with the soft information being obtained by removing the user mask; according to the Viterbi 0 state accumulated metric of each HS-SCCH and the sum of absolute values of the corresponding soft information, obtaining determination variables of each HS-SCCH; selecting the maximum from the determination variables of HS-SCCH, comparing the maximum with the preset threshold, and determining whether the HS-SCCH of this user is detected. | ||||||
| 142 | METHOD AND APPARATUS FOR VEILING AND DETECTING DATA USING AN ERROR CORRECTING CODE | US13591894 | 2012-08-22 | US20130055045A1 | 2013-02-28 | Seho Myung; Bogyeong Kang |
| An apparatus and method for veiling protected data in a memory is provided. The method includes encoding protected data using an Error Correcting Code (ECC); inserting a progression to the encoded protected data according to a preset rule; combining an error with the progression-inserted protected data; and storing the error-combined protected data in an arbitrary position in the memory. | ||||||
| 143 | Data modulating device and method thereof | US12689100 | 2010-01-18 | US08365035B2 | 2013-01-29 | Masaaki Hara |
| A data modulating device includes: an LDPC encoding unit configured to execute LDPC encoding; and a balance encoding unit configured to input a data string subjected to encoding by the LDPC encoding unit as data to be encoded, and convert k bits of this data to be encoded into balance code made up of m-bit block data; with the balance encoding unit executing balance encoding of said data to be encoded using a data conversion table subjected to mapping so that a set of the k-bit data patterns of which the Hamming distance is 1 corresponds to a set of block data of which the Hamming distance is 2. | ||||||
| 144 | SEMICONDUCTOR DEVICE AND METHOD OF WRITING DATA TO SEMICONDUCTOR DEVICE | US13523969 | 2012-06-15 | US20120324310A1 | 2012-12-20 | Daisuke OSHIDA; Shigeru Furuta; Masayuki Hirokawa; Akira Yamazaki; Takashi Fujimori; Shigemasa Shiota |
| A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information. | ||||||
| 145 | Systems and methods for retimed virtual data processing | US12540283 | 2009-08-12 | US08266505B2 | 2012-09-11 | Jingfeng Liu; Hongwei Song |
| Various embodiments of the present invention provide systems and methods for data processing system. As one example, a data processing circuit is described that includes an analog to digital converter, an online timing loop, and an offline timing loop. The analog to digital converter receives an analog input and provides a first series of data samples Each bit of the first series of data samples corresponds to the analog input at a time controlled by an updated sampling clock. The online timing loop modifies the updated sampling clock based at least in part upon a processed version of the first series of data samples. The offline timing loop interpolates a derivative of the first series of data samples to yield a second series of data samples that mimics a series of data samples corresponding to the analog input that were sampled using a free running clock. The second series of data samples is interpolated to adjust each bit in accordance with an average frequency offset exhibited across the second series of data samples. | ||||||
| 146 | ENCODING DEVICE FOR ERROR CORRECTION, ENCODING METHOD FOR ERROR CORRECTION AND ENCODING PROGRAM FOR ERROR CORRECTION | US13438564 | 2012-04-03 | US20120192040A1 | 2012-07-26 | Mitsuru HAMADA |
| The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with an aspect of the present invention there is provided an encoding device for error correction, the device comprises a generation means for generating randomly a vector u=(xk+1, . . . xm) composed of m-k digit(s); a creation means for creating an x′=[xu]=(x1, . . . , xm) by concatenating the vector u=(xk+1, . . . , xm) composed of m-k digit(s) randomly created by the creation means to data x=(x1, . . . , xk) to send; and an output means for outputting a vector of length n by carrying out [n, m] encoding of the x′ created by the creation means. | ||||||
| 147 | Architecture and control of reed-solomon list decoding | US12541720 | 2009-08-14 | US08132083B1 | 2012-03-06 | Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Ichiro Kikuchi; Tony Yoon |
| Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | ||||||
| 148 | Architecture and control of Reed-Solomon error-correction decoding | US12249474 | 2008-10-10 | US08132082B2 | 2012-03-06 | Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Ichiro Kikuchi; Tony Yoon |
| Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | ||||||
| 149 | Techniques to perform forward error correction for an electrical backplane | US12964271 | 2010-12-09 | US08108756B2 | 2012-01-31 | Ilango S. Ganga; Luke Chang; Andrey Belogolovy; Andrei Ovchinnikov |
| Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. | ||||||
| 150 | Communication apparatus and method including a plurality of descramblers | US11909687 | 2006-04-27 | US08099653B2 | 2012-01-17 | Tetsuo Kanda; Tadashi Eguchi |
| A communication apparatus includes a plurality of descramblers for subjecting a second header portion of a received frame to descrambling processing using pseudo-random sequences that differ from one another; a plurality of syndrome arithmetic units for performing a syndrome calculation, which is in accordance with a cyclic redundancy check code, with respect to headers descrambled by respective ones of the plurality of descramblers, and an error correction unit for selecting a header that has been descrambled by one descrambler among the plurality of descramblers as a receive header, in accordance with syndrome values calculated by respective ones of the plurality of syndrome arithmetic units. | ||||||
| 151 | VIRTUAL COPY AND VIRTUAL WRITE OF DATA IN A STORAGE DEVICE | US12828029 | 2010-06-30 | US20120005557A1 | 2012-01-05 | Eitan Mardiks; Eran Erez |
| A storage device with a memory and a controller, and a method of copying data on a storage device are provided to perform virtual copy and virtual write of data in a storage device without physically storing data in the storage device. The controller includes, or incorporates with an executable module that handles a command to copy data from a source logical address to a destination logical address, where the source logical memory address data is already associated with a first physical memory address storing the data. | ||||||
| 152 | Techniques to perform forward error correction for an electrical backplane | US12639797 | 2009-12-16 | US07873892B2 | 2011-01-18 | Ilango S. Ganga; Luke Chang; Andrey Belogolovy; Andrei Ovchinnikov |
| Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. | ||||||
| 153 | Techniques to perform forward error correction for an electrical backplane | US11325765 | 2006-01-04 | US07676733B2 | 2010-03-09 | Ilango S. Ganga; Luke Chang; Andrey Belogolovy; Andrei Ovchinnikov |
| Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. | ||||||
| 154 | Coding Apparatus, Coding Method and Coding Program | US12470607 | 2009-05-22 | US20090300462A1 | 2009-12-03 | Keitarou Kondou; Makoto Noda |
| Disclosed herein is an encoding apparatus which combines an RLL code word and an error correction code word, with an interleaving technique when encoding, including: an error correction encoding section; an interleaving section; and an RLL encoding section, wherein, if an address i (i is an integer satisfying relations 0≦i |
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| 155 | DIGITAL BROADCAST TRANSMITTER AND RECEIVER AND METHOD FOR PROCESSING STREAM THEREOF | US12427005 | 2009-04-21 | US20090274242A1 | 2009-11-05 | Yong-sik KWON; June-hee LEE |
| A digital broadcast receiver is provided. The digital broadcast receiver includes a receiver which receives a transport stream transmitted from a digital broadcast transmitter, an additional data stream detector which determines whether the received transport stream includes an additional data stream or not, and a processor which process the additional data stream if the transport stream include the additional data stream, and the transport stream including the additional data stream is a transport stream into which a training signal is inserted by the digital broadcast transmitter which resets memories used for trellis-encoding at predetermined time. Accordingly, it is easily detected whether the transport stream includes the additional data stream or not. | ||||||
| 156 | Architecture and control of Reed-Solomon error identification and evaluation | US11195403 | 2005-08-01 | US07590923B1 | 2009-09-15 | Ichiro Kikuchi; Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Tony Yoon |
| Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | ||||||
| 157 | METHOD OF ENCODING AND DECODOING | US12465747 | 2009-05-14 | US20090228759A1 | 2009-09-10 | Aalbert Stek; Cornelis Marinus Schep; Martinus Wilhelmus Blum |
| The invention relates to a method of encoding user data into codevectors and to a corresponding method of decoding codevectors into user data. In order to be able to use the same ECC decoder for decoding of more than one type of data a method of encoding is proposed comprising the steps of: generating a first block of a fixed first number of data symbols by taking a fixed second number, being smaller than said first number, of user data symbols, and a fixed third number of dummy data symbols, and by arranging said user data symbols and said dummy data symbols in a predetermined order, encoding said first block of data symbols using an ECC encoder (2) to obtain a codeword having a fixed number of symbols, said codeword comprising said first block of data symbols and a second block of a fixed forth number of parity symbols, and generating a codevector by selecting a fifth predetermined number of user data symbols and a sixth predetermined number of parity symbols from said codeword, the sum of said fifth and sixth number being predetermined and smaller than the sum of said second and forth number. | ||||||
| 158 | Decoding method, medium, and apparatus | US11050768 | 2005-02-07 | US07487423B2 | 2009-02-03 | Austin Lobo; Sang-rae Lee |
| A decoding method, medium, and apparatus capable of preventing error propagation and implementing parallel processing. A decoding method includes comparing encoding information with decoding information at synchronization points for detecting a transmission error, and continuing to decode the encoded data if both the encoding and decoding information match, or continuing to decode remaining data located beyond the corresponding synchronization point by limiting a transmission error region to between the corresponding synchronization point and an immediately previous synchronization point, with reference to the encoding information if the encoding and decoding information do not match. Furthermore, the encoded data of a plurality of regions are simultaneously decoded in parallel, with reference to the encoding information of a plurality of synchronization points. Therefore, it is possible to prevent error propagation by limiting the transmission error within a smallest possible length and to reduce a decoding time by using a parallel processing. | ||||||
| 159 | LOW COMPLEXITY ENCRYPTION METHOD FOR CONTENT THAT IS CODED BY A RATELESS CODE | US12055934 | 2008-03-26 | US20080317243A1 | 2008-12-25 | Sean A. Ramprashad |
| A method and apparatus is disclosed herein for a low complexity method of securing content that is coded by a rateless code whereby it is noted that it is sufficient to encrypt only a subset of the ratelessly coded packets. In one embodiment, the method comprises performing rateless coding on a first set of blocks of data to produce ratelessly encoded blocks of data and performing encryption on a subset of the ratelessly encoded blocks of data based on a degree value for each of the ratelessly encoded blocks of data. | ||||||
| 160 | Architecture and control of reed-solomon list decoding | US11195183 | 2005-08-01 | US07454690B1 | 2008-11-18 | Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Ichiro Kikuchi; Tony Yoon |
| Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | ||||||
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