| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | DUPLEX TRANSMISSION OVER REDUCED PAIRS OF TWINAX CABLES | US14179727 | 2014-02-13 | US20150326379A1 | 2015-11-12 | Dariush Dabiri; Tarun Gupta; Venkatesh Nagapudi |
| Cable systems and assemblies integrate a reduced number of twin axial copper pairs to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial copper pairs comprise four or less twin axial copper pairs, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals. A processor can be integrated with the twin axial copper pairs operate to encode the signals for fast transmission speeds. | ||||||
| 182 | High speed transceiver based on embedded leech lattice constellation | US14466334 | 2014-08-22 | US09172578B1 | 2015-10-27 | Dariush Dabiri |
| A transceiver architectures can comprises an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on a leech lattice. The data can be transmitted at a high speed according to the constellation with an embedded leech lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency. | ||||||
| 183 | Use of parity-check coding for carrier-phase estimation in an optical transport system | US14105854 | 2013-12-13 | US09166628B2 | 2015-10-20 | Timo J. Pfau |
| An optical transport system is configured to use a modulation scheme in which a phase rotation applied to a sequence of PSK or QAM constellation symbols encoding a codeword of an FEC code produces a modified sequence of PSK or QAM constellation symbols encoding a bit-word that is not a valid codeword of that FEC code. Based on this property of the modulation scheme, an optical receiver may be configured to relatively accurately recover the absolute phase of the optical carrier wave of the received modulated optical signal by applying maximum likelihood sequence estimation processing to each portion of the signal carrying a valid codeword of the FEC code. For example, for a modulation scheme employing a 2n-PSK constellation, the optical receiver may be able to recover the absolute phase of the optical carrier wave with an accuracy that is better than 360/2n degrees. | ||||||
| 184 | Detection and handling of unbalanced errors in interleaved codewords | US14024531 | 2013-09-11 | US09092350B1 | 2015-07-28 | Seungjune Jeon; Xiaoheng Chen |
| Mechanisms are provided for detecting whether at least one of two or more portions of memory (e.g. chips, blocks, sectors, planes, pages, word lines, etc.) are more error-prone than the others, when portions of codewords are interleaved across the two or more portions of memory. Some implementations also enable various remedial operations that can be selectively employed in response to detecting an unbalanced error condition in order to reduce the risks associated with interleaving portions of codewords across two or more portions of memory. | ||||||
| 185 | RECEIVER, TRANSMITTER, AND COMMUNICATION METHOD | US14417447 | 2013-08-27 | US20150195081A1 | 2015-07-09 | Wataru Matsumoto; Toshiaki Akino; Yoshikuni Miyata; Kenya Sugihara; Takashi Sugihara; Takafumi Fujimori |
| A transmitter for transmitting a transmission signal subjected to modulation after error correction coding and a receiver including a phase compensation unit for receiving the transmission signal and performing demodulation therefor while maintaining synchronization thereof and an error correction decoding unit for performing decoding processing for received data that has been subjected to the demodulation. The transmitter transmits a signal formed of a plurality of pilot sequences as a part of the transmission signal, and the receiver has a phase slip estimation processing function for estimating the phase slip by the phase compensation unit by using the plurality of pilot sequences, and for estimating a phase difference component by the error correction decoding unit, to thereby correct a phase of the received data. | ||||||
| 186 | Techniques to perform forward error correction for an electrical backplane | US13733271 | 2013-01-03 | US09047204B2 | 2015-06-02 | Ilango S. Ganga; Luke Chang; Andrey Belogolovy; Andrei Ovchinnikov |
| Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator. | ||||||
| 187 | DATA ENCODING IN SOLID-STATE STORAGE APPARATUS | US14496416 | 2014-09-25 | US20150149872A1 | 2015-05-28 | Thomas Mittelholzer; Nikolaos Papandreou; Charalampos Pozidis |
| A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of qary symbols via a first drift-tolerant encoding scheme, the preliminary block comprising the first group of qary symbols and any remainder of the input block not encoded via the first encoding scheme; generating parity data for the preliminary block via an error-correction encoding scheme; modulation encoding the parity data and any remainder of the input block into a second group of qary symbols via a second drift-tolerant encoding scheme; and supplying the qary symbols of the first and second groups for storage in respective q-level memory cells. | ||||||
| 188 | Adaptation of analog memory cell read thresholds using partial ECC syndromes | US13743721 | 2013-01-17 | US08869008B2 | 2014-10-21 | Barak Baum; Micha Anholt |
| A method includes storing data that is encoded with an Error Correction Code (ECC) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds. The memory cells in the group are divided into two or more subsets. N partial syndromes of the ECC are computed, each partial syndrome computed over readout results that were read using a respective set of the read thresholds from a respective subset of the memory cells. For each possible N-bit combination of N bit values at corresponding bit positions in the N partial syndromes, a respective count of the bit positions in which the combination occurs is determined, so as to produce a plurality of counts. An optimal set of read thresholds is calculated based on the counts, and data recovery is performed using the optimal read thresholds. | ||||||
| 189 | METHOD AND SYSTEM FOR OPERATING A COMMUNICATION CIRCUIT CONFIGURABLE TO SUPPORT ONE OR MORE DATA RATES | US13733798 | 2013-01-03 | US20140189459A1 | 2014-07-03 | Divya Vijayaraghavan; Chong H. Lee; Keith Duwel; Vinson Chan |
| A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module. | ||||||
| 190 | Method of encoding and decoding | US12465747 | 2009-05-14 | US08683300B2 | 2014-03-25 | Aalbert Stek; Cornelis Marinus Schep; Martinus Wilhelmus Blum |
| The invention relates to a method of encoding user data into codevectors and to a corresponding method of decoding codevectors into user data. In order to be able to use the same ECC decoder for decoding of more than one type of data a method of encoding is proposed comprising the steps of: generating a first block of a fixed first number of data symbols by taking a fixed second number, being smaller than said first number, of user data symbols, and a fixed third number of dummy data symbols, and by arranging said user data symbols and said dummy data symbols in a predetermined order, encoding said first block of data symbols using an ECC encoder (2) to obtain a codeword having a fixed number of symbols, said codeword comprising said first block of data symbols and a second block of a fixed forth number of parity symbols, and generating a codevector by selecting a fifth predetermined number of user data symbols and a sixth predetermined number of parity symbols from said codeword, the sum of said fifth and sixth number being predetermined and smaller than the sum of said second and forth number. | ||||||
| 191 | Method for Control Channel Detection in Wireless Communications Systems | US13542752 | 2012-07-06 | US20140012399A1 | 2014-01-09 | Jens Berkmann; Armin Haeutle; Axel Huebner |
| A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the received data. A decision metric representing a sum or a difference of the path metric and the correction term is computed. Based on the decision metric, it is decided on a detection of the control channel. | ||||||
| 192 | METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) CODING FOR SCRAMBLED CODED MULTIPLE ACCESS (SCMA) | US13791949 | 2013-03-09 | US20130198581A1 | 2013-08-01 | Lin-Nan LEE; Mustafa EROZ |
| A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals. | ||||||
| 193 | Encoding device for error correction, encoding method for error correction and encoding program for error correction | US13438564 | 2012-04-03 | US08365052B2 | 2013-01-29 | Mitsuru Hamada |
| The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with an aspect of the present invention there is provided an encoding device for error correction, the device comprises a generation means for generating randomly a vector u=(xk+1, . . . , xm) composed of m-k digit(s); a creation means for creating an x′=[xu]=(x1, . . . , xm) by concatenating the vector u=(xk+1, . . . , xm) composed of m-k digit(s) randomly created by the creation means to data x=(x1, . . . , k) to send; and an output means for outputting a vector of length n by carrying out [n, m] encoding of the x′ created by the creation means. | ||||||
| 194 | Method of Identifying and Protecting the Integrity of a Set of Source Data | US13514178 | 2010-10-05 | US20130019140A1 | 2013-01-17 | Cleon L. Rogers, JR.; Glen T. Logan |
| A method of identifying and protecting the integrity of a set of source data which produces and combines an identification signature with a detection and correction remainder and extends the existing capability of some information assurance methods. | ||||||
| 195 | Techniques to perform forward error correction for an electrical backplane | US13348341 | 2012-01-11 | US08352828B2 | 2013-01-08 | Ilango S. Ganga; Luke Chang; Andrey Belogolovy; Andrei Ovchinnikov |
| Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction. | ||||||
| 196 | Architecture and control of Reed-Solomon error-correction decoding | US13364802 | 2012-02-02 | US08296635B2 | 2012-10-23 | Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Ichiro Kikuchi; Tony Yoon |
| Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | ||||||
| 197 | Architecture and control of reed-solomon error identification and evaluation | US12512710 | 2009-07-30 | US08245118B2 | 2012-08-14 | Ichiro Kikuchi; Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Tony Yoon |
| Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | ||||||
| 198 | Architecture and control of reed-solomon error-correction decoding | US12324285 | 2008-11-26 | US08219894B2 | 2012-07-10 | Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Ichiro Kikuchi; Tony Yoon |
| Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | ||||||
| 199 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING | US13364802 | 2012-02-02 | US20120137197A1 | 2012-05-31 | Siu-Hung Fred Au; Gregory Burd; Zining Wu; Jun Xu; Ichiro Kikuchi; Tony Yoon |
| Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | ||||||
| 200 | Method and apparatus for channel encoding and decoding in a communication system using low-density-parity-check codes | US12393670 | 2009-02-26 | US08176384B2 | 2012-05-08 | Seho Myung; Hwan-Joon Kwon; Kyung-Joong Kim; Kyeong-Cheol Yang; Hyun-Koo Yang; Jae-Yoel Kim; Hak-Ju Lee |
| A method and apparatus for encoding and decoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The encoding method includes determining a modulation scheme for transmitting a symbol; determining a shortening pattern in consideration of the determined modulation scheme; grouping columns corresponding to an information word in a parity-check matrix of the LDPC code into a plurality of column groups; ordering the column groups; determining a range of a resulting information word desired to be obtained by shortening the information word; based on the range of the resulting information word, performing column group-by-column group shortening on the ordered column groups of the information word, according to the determined shortening pattern; and LDPC-encoding the shortened information word. | ||||||
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