| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 201 | Method and Apparatus for Adapting Data To a Transport Unit of a Predefined size prior to transmission | US11988294 | 2006-06-19 | US20100005369A1 | 2010-01-07 | Peter Farkas |
| An apparatus and a method for adapting data in a communications system to be transmitted from a sender to a receiver, to a transport unit of a predefined size involve representing said data as a combination of bits over a finite field, wherein said data comprises of an information part and a control part; adapting said represented data to fit said predefined size of said transport unit, by expressing both said information and control parts with bits, wherein said bits are less in number that said represented combination of bits and a number of removed bits is known to said receiver, said removed bits comprise of bits from both said information and control parts. | ||||||
| 202 | In-place transformations with applications to encoding and decoding various classes of codes | US11423376 | 2006-06-09 | US07644335B2 | 2010-01-05 | Michael G. Luby; M. Amin Shokrollahi |
| In an encoder for encoding symbols of data using a computing device having memory constraints, a method of performing a transformation comprising loading a source block into memory of the computing device, performing an intermediate transformation of less than all of the source block, then replacing a part of the source block with intermediate results in the memory and then completing the transformation such that output symbols stored in the memory form a set of encoded symbols. A decoder can perform decoding steps in an order that allows for use of substantially the same memory for storing the received data and the decoded source block, performing as in-place transformations. Using an in-place transformation, a large portion of memory set aside for received data can be overwritten as that received data is transformed into decoded source data without requiring a similar sized large portion of memory for the decoded source data. | ||||||
| 203 | Systems and processes for decoding a chain reaction code through inactivation | US11842102 | 2007-08-20 | US07633413B2 | 2009-12-15 | M. Amin Shokrollahi; Soren Lassen; Richard Karp |
| A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one. | ||||||
| 204 | Auto suggestion of coding error correction | US10183259 | 2002-06-26 | US07607066B2 | 2009-10-20 | Matthew Wayne Gertz; Sam Spencer; Ernest Kien-Keung Tong; Li Zhang |
| Suggested corrections for a code error are provided by a compiler or code editor, for example. Thus, there is much less ambiguity about how an error should be corrected. Preferably, a predetermined number of suggested corrections are presented to the user (e.g., up to three suggestions), and the user can choose a desired suggested correction. Corrections for a given error can be made, not only at the location of the error, but throughout the code document, or other files in the user's solution. Furthermore, by undoing one correction and trying another, the user can go through all of the suggested corrections to determine which suggestion would be most preferable. | ||||||
| 205 | Method and apparatus for non-linear scaling of log likelihood ratio (LLR) values in a decoder | US11239274 | 2005-09-29 | US07555071B2 | 2009-06-30 | Uwe Sontowski |
| Methods and apparatus are provided for non-linear scaling of log likelihood ratio (LLR) values in a decoder. A decoder according to the present invention processes a received signal by generating a plurality of log-likelihood ratios having a first resolution; applying a non-linear function to the plurality of log-likelihood ratios to generate a plurality of log-likelihood ratios having a lower resolution; and applying the plurality of log-likelihood ratios having a lower resolution to a decoder. The non-linear function can distribute the log-likelihood ratios, for example, such that the frequency of each LLR value is more uniform than a linear scaling. | ||||||
| 206 | CRC-based error correction | US10515809 | 2002-05-24 | US07496825B2 | 2009-02-24 | Niels Degn |
| An ordered list of CRC syndromes, corresponding to single-bit errors, is used to identify an error bit position, enabling correction of the bit at the identified error bit position. For instance, the syndrome corresponding to an error at the fifth bit position is in the fifth position in the list. A syndrome for a received block is compared sequentially with the members of the list until a match is found. When a match is found, the corresponding bit of the received block is inverted. | ||||||
| 207 | SYSTEM AND METHOD FOR DIGITAL SIGNAL TRANSMISSION WITH REDUCED ERROR RATE | US12028541 | 2008-02-08 | US20080195923A1 | 2008-08-14 | Kenta MASUMORI |
| A signal processing system is provided with a transmitting-side apparatus transmitting a digital signal, and a receiving-side apparatus receiving the digital signal. The transmitting-side apparatus includes a digital signal transmitter transmitting the digital signal and a signal controller controlling the digital signal. The receiving-side apparatus includes a digital signal receiver receiving the digital signal, an error rate detector detecting the error rate of the digital signal received, and a receiving-side controller transmitting error rate data based on the detected error rate to the transmitting-side apparatus. The transmitting-side apparatus further includes a transmitting-side controller receiving the error rate data and controlling the signal controller in response to the error rate data. | ||||||
| 208 | Channel Coding Method with Corresponding Code and Demodulation and Decoding Method and Means | US11573321 | 2005-08-08 | US20070210943A1 | 2007-09-13 | Ing. Hermann Tropf |
| A coding/decoding system and method are disclosed. Coding, as used herein, refers assigning values to cells. Information to be coded is processed stepwise in information pieces, with bitwise processing (single information bits as information pieces) as a special case. According to an illustrative embodiment, bitwise coding/decoding is disclosed. A predefined structure called a configuration is known to both the coding and decoding systems. The configuration includes a step configuration for each coding step. A step configuration is: 1) a distinction of two subsets of cells, one called inversion cells, the other called non inversion cells; 2) an assignment of at least one cell tuple consisting of at least one inversion cell and one non inversion cell each, where, for these tuples, for any preceding step configuration the tuple cells are either all inversion cells or all non inversion cells. For coding, in each step, its inversion cells are XORed with the information bit. For decoding, the information bits are recovered in reverse order. In each step, its step configuration is used; the information bit is recovered by tuplewise comparing inversion cells with non inversion cells. If, for a majority of cell tuples, the cells are different, the information bit is set, otherwise it is not set. If it is set, the inversion cells are inverted for further decoding steps, if any. The method provides for easy application specific integration of demodulation into decoding and for introduction of soft decision methods. Robust decoding is achieved by means of majority decisions. | ||||||
| 209 | Data transmission method and data transmission device | US10148997 | 2001-10-29 | US07184479B2 | 2007-02-27 | Tomohiro Takano; Tadashi Sakaguchi; Hideyuki Azumi |
| A data transmission method capable of suppressing communication errors with a simple microcomputer processing is provided. Upon a pulse signal in which specific data is made up of H and L levels, either one of which has a pulse width taken as a first fundamental signal length T1 and the other of which has a pulse width taken as a second fundamental signal length T2 equal to an integer multiple of the first fundamental signal length T1, a correction is performed by increasing or decreasing the second fundamental signal length T2 by a length equal to an integer multiple of a value resulting from dividing the first fundamental signal length T1 of the transmission-side pulse signal by an integer. | ||||||
| 210 | Method for forming rate compatible code using high dimensional product codes | US10547236 | 2003-12-30 | US20060190271A1 | 2006-08-24 | Soo Kim; Deock-Gil Oh; Jae-Moung Kim |
| Provided is a method for forming a rate compatible code using high dimensional product codes and a computer-readable recording medium for recording a program that implements the program. The rate compatible code, which can provide various encoding rates, is formed by discriminating parity blocks and determining a punctured pattern for each parity block, m being more than two. The method includes the steps of: a) forming an m dimensional product code by using a systematic block code; b) dividing the m dimensional product code into an information block and 2m-1 parity blocks; c) allocating indices to the divided blocks of the information block and 2m-1 parity blocks; d) finding all combinations of the information block and the parity blocks which are adjacent to the information block; e) estimating a first weighting factor of w1 for the all combinations; f) if there are first combinations having the same weighting factor w1, estimating a second weighting factor of w2 for the first combinations having the same weighting factor w1 as second combinations; g) selecting a combination having largest weighting factor among the second combinations having the second weighting factor w2; and h) forming rate compatible codes by using the selected combinations based on the w1 and w2. | ||||||
| 211 | Data redundancy methods and apparatus | US10371628 | 2003-02-20 | US07093182B2 | 2006-08-15 | Lawrence John Dickson |
| Method and apparatus for providing data recovery in a one or multiple disk loss situation in a RAID5 like system. A data storage apparatus has a plurality of n disks storing data comprising a plurality of n data groupings stored across the plurality of n disks. Each one of the n data groupings comprises a data portion and a redundancy portion. The size of the data portion relative to the redundancy portion is as H to Q, where H/Q<(n−m)/m, where m is the maximum number of disks that may be lost at any given time. Advantageously, the n data portions are recoverable from any and all combinations of n-m data grouping(s) on n−m disk(s) when the other m data grouping(s) are unavailable, where 1≦m | ||||||
| 212 | Method and apparatus for protecting lossless transmission of a data stream | US10046991 | 2002-01-15 | US07028249B2 | 2006-04-11 | Alphons Antonius Maria Lambertus Bruekers; Adriaan Johannes Rijnberg; Bernard Van Steenbrugge; Marcel Stefan Emmanuel Van Nieuwenhoven |
| A method and apparatus for encoding an input digital signal for lossless transmission comprising first calculation means for calculating a checksum of the input digital signal. The apparatus further comprises encoding means for lossless encoding into an encoded packet of digital data, and composition means for adding the associated checksum to the encoded packet to form an encoded signal. Associated are a method and apparatus for decoding the encoded signal, comprising extracting means for receiving the encoded signal and extracting the encoded packet and associated checksum, decoding means for decoding the encoded packet into a decoded packet comprising the input digital signal, second calculation means for calculating a checksum for the decoded packet, and output means for outputting the decoded packet as an output signal if the calculated checksum corresponds with the extracted checksum. | ||||||
| 213 | Correlation matrix learning method and apparatus, and storage medium therefor | US09962090 | 2001-09-26 | US07024612B2 | 2006-04-04 | Naoki Mitsutani |
| In an associative matrix training method, calculation between a code word and an associative matrix is performed. The calculation result is compared with a threshold value set for each component on the basis of an original word. The associative matrix is updated on the basis of the comparison result using an update value which changes stepwise. Training of the associative matrix including calculation, comparison, and update is performed for all code words, thereby obtaining an optimum associative matrix for all the code words. An associative matrix training apparatus and storage medium are also disclosed. | ||||||
| 214 | Method of reducing miscorrections in a post-processor using column parity checks | US10015181 | 2001-11-20 | US06986098B2 | 2006-01-10 | Alan D. Poeppelman; David L. Schell; Kevin G. Christian |
| The present invention is a method and system for reducing miscorrections of data in a post-processor. In an embodiment of the invention, the system and method may compare a result of an exact match function and a metric for each row of a reconstructed data block to determine if a correction should be made. An algorithm for performing an exact match function may include a column parity check syndrome, a matched filter error syndrome, and an error mask of the present invention. If a result of an exact match function is an exact match, a priority of correction may be given to the row in which the exact match was produced. | ||||||
| 215 | Method and apparatus for generating parity bits in a forward error correction (FEC) system | US10371560 | 2003-02-21 | US06986097B1 | 2006-01-10 | Howard H. Ireland; Jeffery T. Nichols |
| A method and apparatus for performing parity bit generation. The apparatus of the present invention comprises a parity bit generator that multiplies words comprising message bits by a partial parity multiplication sub-matrix to generate intermediate parity values, and recursively adds (modulo-2) respective intermediate values together so that by the end of the recursive process, a final parity vector exists. This final parity vector can then be added to a message word to create a code word. By recursively using the partial parity multiplication sub-matrix in this way, the number of gates needed to perform parity bit generation is kept relatively small. Consequently the amount of power consumed by the parity bit generator during parity bit generation is relatively small. This is in contrast to typical parity bit generators, which multiply all of the message bits by a full parity multiplication matrix without recursion. The typical non-recursive process, which utilizes the complete parity multiplication matrix, requires a very large number of gates and a large area on an IC to implement the parity bit generator. Also, because of the large number of gates associated with parity bit generators that use the typical approach, those generators consume a large amount of power. The method and apparatus of the present invention are suitable for use with an encoder of a forward error correction (FEC) system. | ||||||
| 216 | Systems and processes for decoding a chain reaction code through inactivation | US11031331 | 2005-01-07 | US20050206537A1 | 2005-09-22 | M. Shokrollahi; Soren Lassen; Richard Karp |
| A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one. | ||||||
| 217 | Bit error concealment methods for speech coding | US11111821 | 2005-04-22 | US20050187764A1 | 2005-08-25 | Juin-Hwey Chen |
| A method of concealing bit errors in a signal is provided. The method comprises encoding a signal parameter according to a set of constraints placed on a signal parameter quantizer. The encoded signal parameter is decoded and compared against the set of c-onstraints. Finally, the method includes declaring the decoded signal parameter invalid when the set of constraints is violated. | ||||||
| 218 | Bit error concealment methods for speech coding | US10222936 | 2002-08-19 | US06885988B2 | 2005-04-26 | Juin-Hwey Chen |
| A method of concealing bit errors in a signal is provided. The method comprises encoding a signal parameter according to a set of constraints placed on a signal parameter quantizer. The encoded signal parameter is decoded and compared against the set of constraints. Finally, the method includes declaring the decoded signal parameter invalid when the set of constraints is violated. Training binned ranges of gain values provide a threshold for selecting data segments to examine for violation of constraints on gain differences. Further, an additional method comprises training a threshold function T(qlg(m−1), Δqlg(m−1) used in a codec bit error detecting technique. The threshold function is based upon a first training file having N signal segments. The method includes encoding the first training file and determining gain values qlg(m) of each of the N signal segments within the encoded first training file. The gain values form a range and the range is divided into bins. Next, the gain values are stored in a second training file. The method associates each of particular ones of the gain values and gain differences within the sequence qlg(m−1) and Δqlg(m−1) with a corresponding one of the bins. | ||||||
| 219 | Commnuication system using correlation matrix, correlation matrix learning method, correlation matrix learning device and program | US10876019 | 2004-06-25 | US20050005221A1 | 2005-01-06 | Naoki Mitsutani |
| A communication system of the present invention comprises a transmission side for transmitting a codeword in which the components of a block encoded codeword are rearranged with a predetermined rule of rearrangement to disperse a redundant portion, and a receiving side for decoding into an original codeword by performing a calculation with a correlation matrix having the row components rearranged with the same rule. This correlation matrix is learned by performing a predetermined calculation using a post-coded codeword and a pre-learned correlation matrix, comparing the components of the calculation result with a preset threshold, and updating the elements of the correlation matrix based on the comparison results to obtain the post-learned correlation matrix. Threshold for learning the correlation matrix is gradually increased as the learning operation proceeds, whereby the optimal threshold to keep the enough margin for bit error is obtained for all of the codewords. Thereby, in transmitting or receiving the block encoded codeword on a radio transmission path, it is possible to reduce the probability that the error correction ability is degraded when a burst bit error (burst error) occurs. | ||||||
| 220 | Method and apparatus for verifying error correcting codes | US10867769 | 2004-06-16 | US20040243887A1 | 2004-12-02 | Debendra Das Sharma; Elizabeth S. Wolf |
| A method and an apparatus verifies the correctness of the error correcting code algorithm and the correctness of the error correcting code implementation. An error injection module is used to inject random errors into an ECC circuit between an encoder and a decoder. The encoder encodes data bits with check bits to produce an encoded signal. A decoder decodes the encoded signal, after modification by the error injection module. The output of the decoder may be a zero error signal, a signal error signal, a multiple error signal, and an error location signal. The output signal is compared to expected values to determine if an error exists in the ECC or the ECC circuit. | ||||||
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