| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 141 | Bit error concealment methods for speech coding | US10222933 | 2002-08-19 | US07406411B2 | 2008-07-29 | Juin-Hwey Chen |
| A system and method of concealing bit errors in a signal are provided. An exemplary method detects bit errors in an input signal having at least a current signal segment and a previous signal segment. The previous signal segment has a log-gain value qlg(m−1) and immediately precedes the current signal segment. The method comprises estimating a level lvl(m−1) of the input signal and determining a log-gain value qlg(m) of the current signal segment within the input signal. The method also comprises determining a difference between the gain value of the current signal segment and the previous signal segment and determining whether the difference exceeds a threshold. wherein the threshold is adaptive to the input signal level. | ||||||
| 142 | Error correcting device, method, and program | US11999446 | 2007-12-04 | US20080155374A1 | 2008-06-26 | Keisuke Tanaka |
| A device, method, and program are provided to prevent an increase of the probability of erroneous correction for a burst error having a length exceeding detection capability even if high correction capability is selected for a random error. In one embodiment, an apparatus corrects errors in a product code block including C1 codes in a row direction and C2 codes in a column direction. First, a C1 decoder performs C1 correction for each of an even C1 including even-numbered bytes in the C1 code and an odd C1 including odd-numbered bytes in the C1 code. Next, a C2 decoder performs erasure correction in C2 correction in the case where any one of the C1 correction results for the even C1 and the odd C1 is correction failure, and where one of the results is the 3-byte correction while the other one is the correction failure or the 3-byte correction. | ||||||
| 143 | Systems and processes for decoding a chain reaction code through inactivation | US11356303 | 2006-02-15 | US07265688B2 | 2007-09-04 | M. Amin Shokrollahi; Soren Lassen; Richard Karp |
| A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one. | ||||||
| 144 | Multi-channel communication method and apparatus using plural Markov Chain Monte Carlo Simulations | US11593899 | 2006-11-06 | US20070076669A1 | 2007-04-05 | Behrouz Boroujeny; Peiman Amini |
| A technique for estimating channel data probability in a multi-user or multiple-input multiple-output communication system is disclosed. The technique uses parallel Markov Chain Monte Carlo simulation to select a plurality of hypothetical channel data patterns. Channel data bit probabilities are obtained by summing conditional bit probabilities, where the conditional bit probabilities are conditioned on an observation of the multi-channel signal and the hypothetical channel data patterns. | ||||||
| 145 | System and method for reviving catastrophic codes | US10090237 | 2002-03-04 | US07170946B2 | 2007-01-30 | Dawei Huang |
| A system and method of the present invention revives a catastrophic code used for channel coding data. A data receiving circuit receives a digital input data sequence to be coded with a code having a distance spectrum containing an infinite component that corresponds to a finite hamming weight such that the code may cause catastrophic error propagation. The circuit is operative for periodically inserting known symbols into the digital input data sequence. An encoder, such as a convolutional encoder, is operatively connected to the data receiving circuit and encodes the digital input data sequence. | ||||||
| 146 | Decoding method and apparatus therefor | US10347524 | 2003-01-21 | US07137045B2 | 2006-11-14 | Sung-hee Hwang; Yoon-woo Lee; Sung-hyu Han; Sang-hyun Ryu; Young-im Ju |
| A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some code words from code words having uncorrectable errors, and performing error correction on code words in the other direction based on the error flags. Accordingly, errors that have been conventionally considered as being uncorrectable may now be corrected. | ||||||
| 147 | Systems and processes for decoding a chain reaction code through inactivation | US11356303 | 2006-02-15 | US20060227022A1 | 2006-10-12 | M. Shokrollahi; Soren Lassen; Richard Karp |
| A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one. | ||||||
| 148 | Method and apparatus for evaluating performance of a read channel | US11068224 | 2005-02-28 | US20060195772A1 | 2006-08-31 | Nils Graef; Zachary Keirn |
| Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time. | ||||||
| 149 | Convolutional coding and decoding method and system | US10259567 | 2002-09-30 | US07080311B2 | 2006-07-18 | Thibault Gallet; André Marguinaud; Brigitte Romann |
| A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.). | ||||||
| 150 | Error detecting code addition circuit, error detection circuit and method, and disc apparatus | US11280431 | 2005-11-17 | US20060156202A1 | 2006-07-13 | Hiroki Takeuchi |
| An error detector includes a substitute value output section outputting a specific substitute value corresponding to an encoding byte sequence Q of input byte data by referring to a table storing, as a substitute value, a value obtained by inputting a substitute code string to a shift register that produces an error detecting value upon input of a code string in an encoding byte sequence Q, a bit processing operation section calculating an error detecting value per byte, and a byte processing operation section outputting an error detecting value of a code string. The substitute code string contains byte data of K number of bytes where only predetermined bit data in byte data corresponding to the encoding byte sequence Q indicates “1” and all other bit data indicates “0”. The bit processing operation section processes each byte data and its substitute value in a different processing sequence from the encoding sequence. | ||||||
| 151 | Systems and processes for decoding a chain reaction code through inactivation | US11031331 | 2005-01-07 | US07030785B2 | 2006-04-18 | M. Amin Shokrollahi; Soren Lassen; Richard Karp |
| A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one. | ||||||
| 152 | Apparatus and method for adaptive, multimode decoding | US09996661 | 2001-11-29 | US07003712B2 | 2006-02-21 | Emin Martinian; Carl-Erik W. Sundberg |
| The present invention provides for adaptive and multimode decoding, in a data packet-based communication system, to provide improved received signal quality in the presence of burst erasures or random bit errors, with particular suitability for real-time, delay sensitive applications, such as voice over Internet Protocol. In the presence of burst erasures, the adaptive multimode decoder of the present invention provides burst erasure correction decoding, preferably utilizes a maximally short (MS) burst erasure correcting code, which has a comparatively short decoding delay. Depending upon the level of such burst erasures, different rate MS codes may be utilized, or other codes may be utilized, such as hybrid or multidescriptive codes. When no burst erasures are detected, the adaptive multimode decoder of the present invention provides random bit error correction decoding, in lieu of or in addition to corresponding burst erasure correction coding. | ||||||
| 153 | Method and apparatus for retaining error-control code protection across block-size discontinuities | US10016440 | 2001-12-11 | US06941503B1 | 2005-09-06 | Michael J. Homberg; Joris Wils; Jack J. Stiffler; Raju C. Bopardikar |
| Each time data, in the form of data blocks protected by code checks, must be reformatted, the original data is broken into new data blocks and a new code check is calculated from, and combined with, each new data block, but the new data blocks and new code checks are both reconstituted versions of the original data blocks and the original code checks. Consequently, the data is never left without protection. In one embodiment, an ingress encoder recomputes an ingress code check from an original data block and its associated header. An egress encoder computes an egress code check from the egress header for an outgoing data block reformatted from the original data block and the ingress code check. The outgoing information is then assembled from the egress header, the outgoing data block and the newly computed egress code check. | ||||||
| 154 | Evaluating and optimizing error-correcting codes using a renormalization group transformation | US09858358 | 2001-05-16 | US06857097B2 | 2005-02-15 | Jonathan S. Yedidia; Jean-Philippe M. Bouchaud |
| A method evaluates an error-correcting code for a data block of a finite size. An error-correcting code is defined by a parity check matrix, wherein columns represent variable bits and rows represent parity bits. The parity check matrix is represented as a bipartite graph. A single node in the bipartite graph is iteratively renormalized until the number of nodes in the bipartite graph is less than a predetermine threshold. During the iterative renormalization, a particular variable node is selected as a target node, and a distance between the target node and every other node in the bipartite graph is measured. Then, if there is at least one leaf variable node, renormalize the leaf variable node farthest from the target node, otherwise, renormalize a leaf check node farthest from the target node, and otherwise renormalize a variable node farthest from the target node and having fewest directly connected check nodes. By evaluating many error-correcting codes according to the method, an optimal code according to selected criteria can be obtained. | ||||||
| 155 | Systems and processes for decoding chain reaction codes through inactivation | US10459370 | 2003-06-10 | US06856263B2 | 2005-02-15 | M. Amin Shokrollahi; Soren Lassen; Richard Karp |
| A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one. | ||||||
| 156 | Method and apparatus for verifying error correcting codes | US09562133 | 2000-05-01 | US06799287B1 | 2004-09-28 | Debendra Das Sharma; Elizabeth S. Wolf |
| A method and an apparatus verifies the correctness of the error correcting code algorithm and the correctness of the error correcting code implementation. An error injection module is used to inject random errors into an ECC circuit between an encoder and a decoder. The encoder encodes data bits with check bits to produce an encoded signal. A decoder decodes the encoded signal, after modification by the error injection module. The output of the decoder may be a zero error signal, a signal error signal, a multiple error signal, and an error location signal. The output signal is compared to expected values to determine if an error exists in the ECC or the ECC circuit. | ||||||
| 157 | Method and apparatus for encoding of linear block codes | US09671372 | 2000-09-26 | US06763492B1 | 2004-07-13 | James Y. Hurt; Jeffrey A. Levin; Nikolai Schlegel |
| A method and apparatus for efficient encoding of linear block codes uses a lookup table including a set of impulse responses to support faster performance by encoding in parallel. Advantages include a scalability that is lacking in existing schemes. | ||||||
| 158 | On-drive integrated sector format raid error correction code system and method | US10301151 | 2002-11-20 | US20040095666A1 | 2004-05-20 | Hideo Asano; Martin Aureliano Hassner; Nyles Norbert Heise; Steven R. Hetzler; Tetsuya Tamura |
| An encoding system and associated method protect against miscorrection due to parity sector correction in, for example, an on-drive RAID system. The system adds a parity cluster block, which itself is a complete, C3-protected cluster. Having the cluster level, C4 level correction, by parity sectors, checked and verified by C3 checks that have high reliability level, as well as the capability for checking consistency of a cluster block, even in the presence of nulljaminull errors, makes this possibility unlikely. A scrub algorithm avoids read-modify-write operations by deferring the completion of the C2 and C3-ckecks until the storage device is idle. | ||||||
| 159 | Analog to digital converter with encoder circuit and testing method therefor | US09906816 | 2001-07-18 | US06653956B2 | 2003-11-25 | Sanroku Tsukamoto |
| A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal. | ||||||
| 160 | Data redundancy methods and apparatus | US10371628 | 2003-02-20 | US20030196023A1 | 2003-10-16 | Lawrence John Dickson |
| Method and apparatus for providing data recovery in a one or multiple disk loss situation in a RAID5 like system. A data storage apparatus has a plurality of n disks storing data comprising a plurality of n data groupings stored across the plurality of n disks. Each one of the n data groupings comprises a data portion and a redundancy portion. The size of the data portion relative to the redundancy portion is as H to Q, where H/Q<(nnullm)/m, where m is the maximum number of disks that may be lost at any given time. Advantageously, the n data portions are recoverable from any and all combinations of n-m data grouping(s) on nnullm disk(s) when the other m data grouping(s) are unavailable, where 1nullm | ||||||
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